Package structure and method of forming thereof

Patent metadata

Field	Value
Publication number	US-10204889-B2
Application number	US-201715409385-A
Country	US
Kind code	B2
Filing date	Jan 18, 2017
Priority date	Nov 28, 2016
Publication date	Feb 12, 2019
Grant date	Feb 12, 2019

Abstract

A package structure includes a semiconductor device, a first dielectric layer, a redistribution line and a conductive bump. The first dielectric layer is over the semiconductor device and has first and second openings on opposite surfaces of the first dielectric layer, wherein the first and second openings taper in substantially opposite direction. The redistribution line is partially in the first opening of the first dielectric layer and electrically connected to the semiconductor device. The conductive bump is partially embeddedly retained in the second opening and electrically connected to the redistribution line.

First claim

What is claimed is:

1. A package structure, comprising:
a semiconductor device;
a first dielectric layer proximate the semiconductor device and having first and second openings between opposite first and second surfaces of the first dielectric layer, wherein the first and second openings taper in substantially opposite directions;
a conductive bump partially embeddedly retained in the second opening;
a redistribution line positioned between the conductive bump and the semiconductor device, inside and outside the first opening of the first dielectric layer, and on the first surface of the first dielectric layer, the redistribution line being electrically connected to the semiconductor device and the conductive bump; and
an under bump metallization structure electrically connected to the conductive bump, wherein the entire under bump metallization structure is inside the second opening of the first dielectric layer.

2. The package structure of claim 1 , further comprising:
a second dielectric layer proximate the first dielectric layer, the second dielectric layer having an opening therein, wherein the conductive bump is partially embeddedly retained in the opening of the second dielectric layer.

3. The package structure of claim 2 , wherein the opening of the second dielectric layer and the first opening of the first dielectric layer taper in substantially opposite directions.

4. The package structure of claim 2 , wherein a roughness of at least one sidewall of the opening of the second dielectric layer is greater than a roughness of a top surface of the second dielectric layer.

5. The package structure of claim 2 , wherein the opening of the second dielectric layer comprises a jagged profile or a rough profile.

6. The package structure of claim 1 , wherein the redistribution line is conformally over the first opening of the first dielectric layer and define a recess.

7. The package structure of claim 1 , wherein the redistribution line defines a recess, and the recess and the second opening taper in substantially opposite directions.

8. The package structure of claim 1 , further comprising:
a third dielectric layer partially embedded in a recess defined by the redistribution line.

9. The package structure of claim 1 , further comprising:
a dielectric structure embedded in a recess defined by the redistribution line, wherein the dielectric structure and the second opening taper in substantially opposite directions.

10. The package structure of claim 1 , further comprising:
a molding material molding the semiconductor device; and
a through-via penetrating through the molding material, wherein the semiconductor device comprises a semiconductor substrate, and the through-via has a surface substantially level with that of the semiconductor substrate.

11. The package structure of claim 1 , wherein the under bump metallization structure is formed conformally over the second opening of the first dielectric layer.

12. The package structure of claim 1 , wherein the under bump metallization structure comprises a cup-shaped portion and a ledge extending from an edge of the cup-shaped portion, wherein the ledge is thicker than the cup-shaped portion.

13. A package structure, comprising:
a semiconductor device;
a first dielectric layer over the semiconductor device and having first and second openings between opposite surfaces of the first dielectric layer;
a redistribution line defining a first recess;
a conductive bump comprising an embedded portion in the second opening of the first dielectric layer, wherein the embedded portion and the first recess taper in substantially opposite directions, wherein the redistribution line is positioned between the conductive bump and the semiconductor device, inside and outside the first opening of the first dielectric layer, and on a surface of the first dielectric layer and the redistribution line is electrically connected to the semiconductor device and the conductive bump; and
an under bump metallization structure including a cup-shaped portion and a ledge that extends from the cup-shaped portion and that is thicker than the cup-shaped portion.

14. The package structure of claim 13 , further comprising:
a metal cup in the second opening of the first dielectric layer, wherein the embedded portion of the conductive bump is embedded in the metal cup.

15. The package structure of claim 14 , further comprising:
a ledge protruding from an outer side of the metal cup, wherein the ledge is thicker than a wall of the metal cup.

16. The package structure of claim 13 , wherein the under bump metallization structure defines a second recess, wherein the embedded portion is in the second recess, and the second recess and the first recess taper in substantially opposite directions.

17. A package structure, comprising:
a semiconductor device;
a first dielectric layer over the semiconductor device;
a redistribution line having a first taper portion embedded in the first dielectric layer through a first surface of the first dielectric layer;
a second dielectric layer over a second surface of the first dielectric layer and having an opening defined by an opening-defining wall; and
a conductive bump having a second taper portion embedded in the first dielectric layer through the opening of the second dielectric layer and the second surface of the first dielectric layer, wherein the first taper portion of the redistribution line and the second taper portion of the conductive bump taper in substantially opposite directions, wherein the redistribution line is positioned between the conductive bump and the semiconductor device and outside of the first dielectric layer on the first surface of the first dielectric layer, the redistribution line is electrically connected to the semiconductor device and the conductive bump, and the conductive bump is in contact with the entire opening-defining wall of the second dielectric layer.

18. The package structure of claim 17 , wherein the second taper portion of the conductive bump has a bottom wider than a top of the first taper portion of the redistribution line.

19. The package structure of claim 17 , further comprising: an under bump metallization structure having a portion between the first taper portion of the redistribution line and the second taper portion of the conductive bump.

20. The package structure of claim 19 , wherein the under bump metallization structure tapers in a direction substantially the same as the direction in which the second taper portion of the conductive bump tapers.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Jing-Cheng
• Tsai Po-Hao

Classifications

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title