Spread spectrum clock generator circuit

Patent metadata

Field	Value
Publication number	US-10200045-B2
Application number	US-201715417434-A
Country	US
Kind code	B2
Filing date	Jan 27, 2017
Priority date	Mar 14, 2016
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A spread spectrum clock generator circuit includes a phase comparator; an oscillator to output an output clock signal; a phase selector to select one of phases equally dividing one cycle of the output clock signal, and to generate a phase shift clock signal having a rising edge in the selected phase; and a phase shift controller to control the phase selector. The phase shift controller generates a variable phase shift amount; determines the phase of the rising edge so that the cycle of the phase shift clock signal has a length changed from the cycle of the output clock signal by the variable phase shift amount added with a fixed phase shift amount; and changes a setting of an SS modulation profile if the selected phase exceeds an upper limit, falls below a lower limit, or is within the upper and lower limits.

First claim

What is claimed is:

1. A spread spectrum clock generator circuit comprising:
a phase comparator configured to detect a phase difference between an input clock signal being a reference and a feedback signal, and to output a control voltage depending on the phase difference;
a voltage-controlled oscillator configured to generate and output an output clock signal having a frequency depending on the control voltage;
a phase selector configured to select one of a predetermined number of phases equally dividing one clock cycle of the output clock signal, to generate a phase shift clock signal having a rising edge in the selected phase, and to transmit the phase shift clock signal to the phase comparator as the feedback signal; and
a phase shift controller configured to control the phase selector,
wherein the phase shift controller generates a second phase shift amount changing periodically within a predetermined range,
calculates a shift amount by adding the second phase shift amount to a first phase shift amount being a center of the shift amount predetermined from the cycle of the output clock signal, and
determines the phase of the rising edge of the phase shift clock signal to be selected by the phase selector, so as to make the cycle of the phase shift clock signal have a length changed from the cycle of the output clock signal by the shift amount,
wherein the phase selector applies a spread spectrum modulation to the output clock signal, depending on the second phase shift amount changing periodically,
wherein the phase shift controller selects the phase having been determined, and changes a setting of an SS modulation profile specifying a step time interval for changing the shift amount, and the shift amount, depending on whether a number to identify the selected phase exceeds an upper limit of the phase selection, falls below a lower limit of the phase selection, or is within the upper and lower limits of the phase selection.

2. The spread spectrum clock generator circuit according to claim 1 , wherein in a case where for executing an SS modulation, for each of a predetermined number of the step time intervals step_p including an SS modulation clock being a minimum time unit to change a shift amount Δph, the shift amount Δph is changed stepwise to be changed in a triangular wave shape approximately,
representing a degree of modulation that represents a maximum change rate of the frequency of the output clock signal, by ss_amp,
representing the frequency in the step time interval step_p, by Δf_step=1/(a number of equal divisions of the output clock signal)/{(a setting value of a division ratio of an output frequency divider+1)×(a setting value of a division ratio of the phase selector circuit+1)},
a maximum value and a minimum value of the predetermined range in which the second phase shift amount changes periodically, are calculated by following formulas:
the maximum value pi _ ssd _max=int( ss _amp/(the number of the equal divisions of the output clock signal×2)/Δ f _step), and

the minimum value pi _ ssd _min=−int( ss _amp/(the number of the equal divisions of the output clock signal×2)/Δ f _step.

3. The spread spectrum clock generator circuit according to claim 2 , wherein the second phase shift amount is calculated by, introducing a count value count(n) that increments every SS modulation clock,
in case of 0≤int(count(n))≤the maximum value of the second phase shift amount:
“the second phase shift amount=int(count( n ))”,

in case of the maximum value of the second phase shift amount<int(count(n))≤the maximum value of the second phase shift amount+(the maximum value of the second phase shift amount−the minimum value of the second phase shift amount):
“the second phase shift amount=the maximum value of the second phase shift amount−{int(count( n ))−the maximum value of the second phase shift amount}”, and

in case of the maximum value of the second phase shift amount+(the maximum value of the second phase shift amount−the minimum value of the second phase shift amount)<int(count(n))<2×(the maximum value of the second phase shift amount−the minimum value of the second phase shift amount):
“the second phase shift amount=the minimum value of the second phase shift amount+{int(count( n ))−(2×the maximum value of the second phase shift amount−the minimum value of the second phase shift amount}”.

4. The spread spectrum clock generator circuit according to claim 3 , wherein in a case where the number to identify the selected phase exceeds the upper limit of the phase selection, the count value “count” is maintained to be a count in a previous cycle.

5. The spread spectrum clock generator circuit according to claim 3 , wherein in a case where the number to identify the selected phase falls below the lower limit of the phase selection, the count value “count” is a count of a previous cycle added with twice Δcount, as represented by a following formula,
count( m )=count( m− 1)+2×{2×(the maximum value of the second phase shift amount−the minimum value of the second phase shift amount)/(an SS modulation cycle/a cycle of the input clock signal)}.

6. A spread spectrum clock generator circuit comprising:
a phase comparator configured to detect a phase difference between an input clock signal being a reference and a feedback signal, and to output a control voltage depending on the phase difference;
a voltage-controlled oscillator configured to generate and output an output clock signal having a frequency depending on the control voltage;
a phase selector configured to select one of a predetermined number of phases equally dividing one clock cycle of the output clock signal, to generate a phase shift clock signal having a rising edge in the selected phase, and to transmit the phase shift clock signal to the phase comparator as the feedback signal; and
a phase shift controller configured to control the phase selector,
wherein the phase shift controller generates a second phase shift amount changing periodically within a predetermined range,
calculates a shift amount by adding the second phase shift amount to a first phase shift amount being a center of the shift amount predetermined from the cycle of the output clock signal, and
determines the phase of the rising edge of the phase shift clock signal to be selected by the phase selector, so as to make the cycle of the phase shift clock signal have a length changed from the cycle of the output clock signal by the shift amount,
wherein the phase selector applies a spread spectrum modulation to the output clock signal, depending on the second phase shift amount changing periodically,
wherein shifting the phase by the phase shift controller starts certainly on a positive side, and control is executed to select a phase in a clock cycle of the feedback signal.

7. The spread spectrum clock generator circuit according to claim 6 , wherein the phase shift controller controls the phase in the clock cycle of the feedback signal, based on a cycle of the input clock into the phase comparator, a division ratio of the clock of the feedback signal, an SS modulation cycle, and a degree of modulation.

8. The spread spectrum clock generator circuit according to claim 6 , wherein in a case where the degree of modulation is set such that a phase out of the cycle of the feedback clock is to be selected, the phase shift controller changes the degree of modulation automatically so as to control selecting a phase in the feedback clock cycle.

9. The spread spectrum clock generator circuit according to claim 1 , wherein an SS modulation cycle is an integer multiple of a cycle of a predetermined synchronization signal, or the cycle of the predetermined synchronization signal i

Assignees

• Sekido Senta
• Ricoh Co Ltd

Inventors

• Sekido Senta

Classifications

• H03L7/081 Primary

  provided with an additional controlled phase shifter {(H03L7/0998 takes precedence)} · CPC title

• H03K4/02

  having stepped portions, e.g. staircase waveform · CPC title

• H03L7/197

  a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division {(H03L7/1806 takes precedence)} · CPC title

• H03L7/0996

  Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator · CPC title

• H03L7/0891

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title