Clock signal generating apparatus, clock signal generating method, and medium

Patent metadata

Field	Value
Publication number	US-9742447-B2
Application number	US-201514969524-A
Country	US
Kind code	B2
Filing date	Dec 15, 2015
Priority date	Dec 26, 2014
Publication date	Aug 22, 2017
Grant date	Aug 22, 2017

Abstract

A clock signal generating apparatus detects a phase difference between an input reference clock signal and a feedback signal to output a control signal based on the phase difference, generates the clock signal with a frequency based on the output control signal, generates a pattern by switching, at a certain time interval, between a plurality of patterns of a second phase shift amount, adds a first phase shift amount to the second phase shift amount having the generated pattern, determines a phase to be selected, so that a cycle of the phase-shifted clock signal matches the cycle of a clock signal changed by the first phase shift amount to which the second phase shift amount is added, selects the determined phase from among a plurality of phases, and generates a phase-shifted clock signal whose signal level changes in the selected phase for output as the feedback signal.

First claim

What is claimed is:

1. A clock signal generating apparatus, comprising:
circuitry configured to:
detect a phase difference between an input reference clock signal serving as a reference and a feedback signal, and output a control signal in accordance with the phase difference;
a generate a clock signal with a frequency in accordance with the control signal;
determine one of a plurality of phases to be selected based on a cycle of the clock signal and a first phase shift amount determined in advance for changing the cycle of the clock signal; and
select the one of the plurality of phases obtained by equally dividing one cycle of the clock signal into a certain number, generate a phase-shifted clock signal whose signal level changes in the selected one of the plurality of phase, and output the generated phase-shifted clock signal as another feedback signal,
wherein the circuitry is configured to generate a pattern by switching, at a certain time interval, between a plurality of patterns of a second phase shift amount that periodically changes every certain time, add the first phase shift amount to the second phase shift amount having the generated pattern, and determine the one of the plurality of phases to be selected so that a cycle of the phase-shifted clock signal matches the cycle of the clock signal changed by the first phase shift amount to which the second phase shift amount having the generated pattern is added.

2. The clock signal generating apparatus according to claim 1 , wherein the plurality of patterns include a plurality of waveform patterns for modulating the clock signal, the plurality of waveform patterns at least including a waveform pattern of a first triangular wave having a certain modulation width.

3. The clock signal generating apparatus according to claim 2 , wherein the plurality of patterns further include a waveform pattern of a second triangular wave having a modulation width smaller than that of the first triangular wave.

4. The clock signal generating apparatus according to claim 2 , wherein the plurality of patterns further include a waveform pattern of a trapezoidal wave obtained by smoothing the first triangular wave so as to eliminate a vertex.

5. The clock signal generating apparatus according to claim 2 , wherein the plurality of patterns further include a waveform pattern of a trapezoidal wave obtained by smoothing a second triangular wave having a modulation width smaller than that of the first triangular wave so as to eliminate a vertex.

6. The clock signal generating apparatus according to claim 1 , wherein the circuitry is configured to select one of a plurality of first parameters for designating a modulation width and one of a plurality of second parameters for designating an increase in the second phase shift amount every modulation clock obtained by equally dividing a modulation cycle of a waveform pattern into a certain number, and, using the selected one of the plurality of first parameters and the selected one of the plurality of second parameters, to generate one of the plurality of patterns.

7. The clock signal generating apparatus according to claim 6 , wherein the circuitry is configured to select a third parameter that controls the modulation width, and generate the one of the plurality of patterns using the selected one of the plurality of first parameters, the selected one of the plurality of second parameters, and the third parameter.

8. The clock signal generating apparatus according to claim 1 , wherein the circuitry is configured to switch between the plurality of patterns at a time where a frequency of a first triangular wave having a certain modulation width, which crosses a reference frequency and which periodically changes, crosses the reference frequency every cycle.

9. A method for generating a clock signal, comprising:
detecting, using circuitry, a phase difference between an input reference clock signal serving as a reference and a feedback signal to output a control signal in accordance with the phase difference;
generating the clock signal with a frequency in accordance with the output control signal;
generating a pattern by switching, at a certain time interval, between a plurality of patterns of a second phase shift amount that periodically changes every certain time;
adding a first phase shift amount to the second phase shift amount having the generated pattern, the first phase shift amount being determined in advance for changing a cycle of the generated clock signal;
determining, using the circuitry, a phase to be selected, so that a cycle of a phase-shifted clock signal matches the cycle of the clock signal changed by the first phase shift amount to which the second phase shift amount having the generated pattern is added;
selecting the determined phase from among a plurality of phases obtained by equally dividing one cycle of the generated clock signal into a certain number; and
generating the phase-shifted clock signal whose signal level changes in the selected determined phase for output as another feedback signal.

10. A non-transitory recording medium which, when executed by one or more processors, cause the processors to perform a method for generating a clock signal, the method comprising:
detecting a phase difference between an input reference clock signal serving as a reference and a feedback signal to output a control signal in accordance with the phase difference;
generating the clock signal with a frequency in accordance with the output control signal;
generating a pattern by switching, at a certain time interval, between a plurality of patterns of a second phase shift amount that periodically changes every certain time;
adding a first phase shift amount to the second phase shift amount having the generated pattern, the first phase shift amount being determined in advance for changing a cycle of the generated clock signal;
determining a phase to be selected, so that a cycle of a phase-shifted clock signal matches the cycle of the clock signal changed by the first phase shift amount to which the second phase shift amount having the generated pattern is added;
selecting the determined phase from among a plurality of phases obtained by equally dividing one cycle of the generated clock signal into a certain number; and
generating the phase-shifted clock signal whose signal level changes in the selected determined phase for output as another feedback signal.

11. The method of claim 9 , wherein the plurality of patterns include a plurality of waveform patterns for modulating the clock signal, the plurality of waveform patterns at least including a waveform pattern of a first triangular wave having a certain modulation width.

12. The method of claim 11 , wherein the plurality of patterns further include a waveform pattern of a second triangular wave having a modulation width smaller than that of the first triangular wave.

13. The non-transitory recording medium of claim 10 , wherein the plurality of patterns include a plurality of waveform patterns for modulating the clock signal, the plurality of waveform patterns at least including a waveform pattern of a first triangular wave having a certain modulation width.

14. The non-transitory recording medium of claim 13 , wherein the plurality of patterns further include a waveform pattern of a second triangular wave having a modulation width smaller than that of the first triangular wave.

15. The clock signal generating apparatus according to claim 1 , wherein the circuitry is configured to generate the clock signal with a phase in accordance with the control signal.

Assignees

• Izawa Yasuhiro
• Ricoh Co Ltd

Inventors

• Izawa Yasuhiro

Classifications

• H03C3/0975

  applying frequency modulation in the phase locked loop at components other than the divider, the voltage controlled oscillator or the reference clock · CPC title

• H04B1/0475 Primary

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

• H04B15/04 Primary

  the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder · CPC title

• H03C3/0916

  with frequency divider or counter in the loop · CPC title

• H03L7/18

  using a frequency divider or counter in the loop (H03L7/20, H03L7/22 take precedence) · CPC title