Isolation of circuit elements using front side deep trench etch

Patent metadata

Field	Value
Publication number	US-10199461-B2
Application number	US-201514924584-A
Country	US
Kind code	B2
Filing date	Oct 27, 2015
Priority date	Oct 27, 2015
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

An integrated circuit is formed by forming an isolation trench through at least a portion of an interconnect region, at least 40 microns deep into a substrate of the integrated circuit, leaving at least 200 microns of substrate material under the isolation trench. Dielectric material is formed in the isolation trench at a substrate temperature no greater than 320° C. to form an isolation structure which separates an isolated region of the integrated circuit from at least a portion of the substrate. The isolated region contains an isolated component. The isolated region of the integrated circuit may be a region of the substrate, and/or a region of the interconnect region. The isolated region may be a first portion of the substrate which is laterally separated from a second portion of the substrate. The isolated region may be a portion of the interconnect region above the isolation structure.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a substrate comprising a semiconductor layer having a top surface;
a first transistor, disposed at the a top surface of the semiconductor layer, in a first portion of the substrate;
a second transistor, disposed at the top surface of the semiconductor layer, in a second portion of the substrate;
a multi-level interconnect region in direct contact with the top surface of the semiconductor layer, the multi-level interconnect region comprising: a dielectric layer; multiple levels of interconnects disposed in the dielectric layer; and vias between the multiple levels of interconnects to electrically couple between the top surface of the semiconductor layer and a top surface of the multi-level interconnect region; and
a solid isolation structure comprising dielectric material in an isolation trench between the first and second transistors, the isolation trench: having a width of at least 5 microns; extending through the top surface of the multi-level interconnect region into the substrate at least 40 microns below the top surface of the semiconductor layer; and having a closed-loop configuration that laterally surrounds the first portion of the substrate and that electrically isolates the first portion of the substrate from the second portion of the substrate; and
at least a third portion of the substrate being under the isolation trench.

2. The integrated circuit of claim 1 , wherein the dielectric material in the isolation trench is selected from the group consisting of an organic polymer, a silicone polymer, an organic silane, a sol gel and a ceramic slurry.

3. The integrated circuit of claim 1 , wherein at least one of the first and second transistors is/are coupled to metal that extends over the solid isolation structure.

4. The integrated circuit of claim 3 , wherein the metal is part of an electronic component.

5. The integrated circuit of claim 4 , wherein the electronic component is a capacitor.

6. The integrated circuit of claim 3 , wherein the first transistor is coupled to the second transistor through the metal.

7. The integrated circuit of claim 6 , wherein the metal is a wire bond.

Assignees

• Texas Instruments Inc

Inventors

• Carothers Dan
• Jackson Ricky
• Mukhopadhyay Rajarshi
• Cook Ben

Classifications

• H10W72/5453

  connecting between multiple bond pads on a chip, e.g. daisy chain · CPC title

• H10W72/536

  the connected ends being ball-shaped · CPC title

• H10W20/496 Primary

  Capacitor integral with wiring layers · CPC title

• H10W20/42

  Vias, e.g. via plugs · CPC title

• H10W10/17

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title