Semiconductor device

Patent metadata

Field	Value
Publication number	US-10199422-B2
Application number	US-201415317094-A
Country	US
Kind code	B2
Filing date	Jul 9, 2014
Priority date	Jul 9, 2014
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

A plurality of pixel regions are aligned in a matrix in a semiconductor substrate, and each of the plurality of pixel regions includes an active region, two photoelectric conversion elements, two floating capacitance regions, and a first transistor. Each of the plurality of pixel regions includes two transfer transistors each having each of the two photoelectric conversion elements and each of the two floating capacitance regions. The first transistor is arranged within the pixel region, between one floating capacitance region and the other floating capacitance region of the two floating capacitance regions with respect to a direction in which the one floating capacitance region and the other floating capacitance region are aligned.

First claim

The invention claimed is:

1. A semiconductor device including a plurality of pixel regions aligned in a matrix in a semiconductor substrate,
each of the plurality of pixel regions including:
one active region formed in the semiconductor substrate;
two photoelectric conversion elements arranged within the one active region to be spaced from each other;
two floating capacitance regions each of which being configured to constitute a transfer transistor for transferring electrons obtained by photoelectric conversion, together with each of the two photoelectric conversion elements, and takes out and accumulates an electric signal output from the photoelectric conversion element; and
a first transistor which receives an electric signal output from the transfer transistor,

each of the plurality of pixel regions including two transfer transistors each including said each of the two photoelectric conversion elements and each of the two floating capacitance regions,
the first transistor being arranged within a pixel region of the pixel regions, between one floating capacitance region and an other floating capacitance region of the two floating capacitance regions with respect to a direction in which the one floating capacitance region and the other floating capacitance region are aligned, and
the first transistor being arranged within the pixel region between one photoelectric conversion element and an other photoelectric conversion element of the two photoelectric conversion elements with respect to a direction in which the one photoelectric conversion element and the other photoelectric conversion element are aligned.

2. The semiconductor device according to claim 1 , wherein said each of the two floating capacitance regions and the first transistor are aligned on a straight line in a plan view.

3. The semiconductor device according to claim 1 , wherein the first transistor is arranged between the active region in a first pixel region and the active region in a second pixel region of the plurality of pixel regions, the first pixel region including the first transistor arranged therein, the second pixel region being adjacent to a side of the first pixel region provided with the one and the other floating capacitance regions when seen from the active region in the first pixel region.

4. The semiconductor device according to claim 3 , wherein the one and the other floating capacitance regions are shared by the first pixel region and the second pixel region.

5. The semiconductor device according to claim 1 , wherein the first transistor includes an amplification transistor which amplifies the electric signals from the two transfer transistors, and
wherein the amplification transistor is shared by the two transfer transistors.

6. The semiconductor device according to claim 5 , wherein each of the plurality of pixel regions further includes a second transistor which receives an electric signal output from the first transistor, and
wherein said each of the two floating capacitance regions and the second transistor are aligned on a straight line in a plan view.

7. The semiconductor device according to claim 6 , wherein the second transistor includes a source region and a drain region, and
wherein at least a portion of any of the source region and the drain region overlaps with any of the two floating capacitance regions.

8. The semiconductor device according to claim 7 , wherein the first transistor includes a first gate electrode,
wherein the second transistor includes a second gate electrode, and
wherein the first gate electrode and the second gate electrode extend in directions intersecting with each other in a plan view.

9. The semiconductor device according to claim 1 , wherein the first transistor includes a reset transistor which resets the electric signal accumulated in the transfer transistor, and
wherein the reset transistor is arranged to be connected to the transfer transistor.

10. The semiconductor device according to claim 1 , wherein the first transistor includes both an amplification transistor which amplifies the electric signals from the two transfer transistors, and a reset transistor which resets the electric signals accumulated in the transfer transistors.

11. The semiconductor device according to claim 1 , wherein each of the two transfer transistors includes a transfer gate electrode, and
wherein the first transistor is arranged within the pixel region, between one transfer gate electrode and an other transfer gate electrode of two transfer gate electrodes with respect to a direction in which the one transfer gate electrode and the other transfer gate electrode are aligned.

12. The semiconductor device according to claim 11 , wherein the first transistor includes an amplification transistor which amplifies the electric signals from the two transfer transistors, and
wherein one amplification transistor is shared by the two transfer transistors.

13. The semiconductor device according to claim 12 , wherein each of the plurality of pixel regions further includes a second transistor which receives an electric signal output from the first transistor, and
wherein said each of the two floating capacitance regions and the second transistor are aligned on a straight line in a plan view.

14. The semiconductor device according to claim 11 , wherein the first transistor includes a reset transistor which resets the electric signal accumulated in the transfer transistor, and
wherein the reset transistor is arranged to be connected to the transfer transistor.

15. The semiconductor device according to claim 11 , wherein the first transistor includes both an amplification transistor which amplifies the electric signals from the two transfer transistors, and a reset transistor which resets the electric signals accumulated in the transfer transistors.

16. The semiconductor device according to claim 1 , wherein the first transistor includes an amplification transistor which amplifies the electric signals from the two transfer transistors, and
wherein one amplification transistor is shared by the two transfer transistors.

17. The semiconductor device according to claim 16 , wherein each of the plurality of pixel regions further includes a second transistor which receives an electric signal output from the first transistor, and
wherein said each of the two floating capacitance regions and the second transistor are aligned on a straight line in a plan view.

18. The semiconductor device according to claim 1 , wherein the first transistor includes a reset transistor which resets the electric signal accumulated in the transfer transistor, and
wherein the reset transistor is arranged to be connected to the transfer transistor.

19. The semiconductor device according to claim 1 , wherein the first transistor includes both an amplification transistor which amplifies the electric signals from the two transfer transistors, and a reset transistor which resets the electric signals accumulated in the transfer transistors.

Assignees

• Renesas Electronics Corp

Inventors

• Araki Yasuhiro

Classifications

• H04N25/778

  comprising amplifiers shared between a plurality of pixels, i.e. at least one part of the amplifier must be on the sensor array itself · CPC title

• H04N25/76

  Addressed sensors, e.g. MOS or CMOS sensors · CPC title

• H01L27/14605

  Electricity · mapped topic

• H01L27/14641

  Electricity · mapped topic

• H01L27/14636

  Electricity · mapped topic