Technique for defining active regions of semiconductor devices with reduced lithography effort

Patent metadata

Field	Value
Publication number	US-10199259-B1
Application number	US-201715670465-A
Country	US
Kind code	B1
Filing date	Aug 7, 2017
Priority date	Aug 7, 2017
Publication date	Feb 5, 2019
Grant date	Feb 5, 2019

Abstract

In semiconductor devices requiring the formation of fully depleted SOI transistor elements in combination with non-FET elements, such as substrate diodes and the like, the patterning of the active regions may be accomplished on the basis of deep isolation trenches, which may be formed first on the basis of immersion-based lithography, followed by formation of shallow isolation trenches also formed on the basis of immersion lithography. Thereafter, respective openings connecting to the substrate materials may be formed, possibly in combination with isolation trenches of reduced depth compared to the deep isolation trenches, on the basis of non-immersion lithography techniques. In this manner, device scaling for semiconductor devices requiring critical dimensions of 26 nm and less in a planar transistor architecture may be accomplished.

First claim

What is claimed:

1. A method, comprising:
forming a first type of isolation trench so as to delineate active regions for transistor elements in a semiconductor layer along a first lateral direction, said first type of isolation trench extending through said semiconductor layer, a buried insulating layer and into a substrate material;
after forming said first type of isolation trench, forming a second type of isolation trench so as to delineate said active regions along a second lateral direction that differs from said first lateral direction, said second type of isolation trench extending to said buried insulating layer; and
after forming said second type of isolation trench, forming an opening so as to expose a portion of said substrate material at a position that is laterally offset from said active region delineated by said first and second types of isolation trench.

2. The method of claim 1 , wherein forming an opening so as to expose a portion of said substrate material comprises forming said opening so as to provide an exposed surface of said substrate material for further processing.

3. The method of claim 1 , wherein forming an opening so as to expose a portion of said substrate material comprises forming said opening by removing a portion of said substrate material and forming a third type of isolation trench extending into said substrate material less than said first type of isolation trench.

4. The method of claim 1 , further comprising filling said first and second types of isolation trench with a dielectric material.

5. The method of claim 4 , wherein said first and second types of isolation trench are filled prior to forming said opening.

6. The method of claim 3 , wherein said first, second and third types of isolation trench are filled prior to forming said opening.

7. The method of claim 1 , wherein said first and second types of isolation trench are formed on the basis of immersion lithography and said opening is formed on the basis of non-immersion lithography.

8. The method of claim 1 , further comprising forming an epitaxially grown semiconductor material on said substrate material.

9. The method of claim 8 , wherein said epitaxially grown semiconductor material is a contact region for electrically connecting to a well region formed below said buried insulating layer at a region that corresponds to said active region.

10. The method of claim 8 , further comprising forming a circuit element in said opening by using said epitaxially grown semiconductor material.

11. The method of claim 1 , wherein forming said first type of isolation trench comprises forming a mask layer stack above said semiconductor layer, patterning an upper portion of said mask layer stack on the basis of a resist mask and patterning a lower portion of said mask layer stack by using said patterned upper portion of said mask layer stack.

12. The method of claim 11 , further comprising adjusting a trench dimension by forming a liner on said patterned upper portion of said mask layer stack prior to patterning said lower portion of said mask layer stack.

13. The method of claim 12 , wherein said liner is formed in one or more deposition processes at a temperature of approximately 100° C. and less.

14. The method of claim 1 , wherein said second type of isolation trench is formed with a width of approximately 30 nm and less.

Assignees

• Globalfoundries Inc

Inventors

• Smith Elliot John
• Zier Michael

Classifications

• H10P50/691

  for Group V materials or Group III-V materials · CPC title

• H10W10/0143 Primary

  comprising concurrently refilling multiple trenches having different shapes or dimensions · CPC title

• H10W10/17 Primary

  formed using trench refilling with dielectric materials, e.g. shallow trench isolations · CPC title

• G03F7/0035

  Multiple processes, e.g. applying a further resist layer on an already in a previously step, processed pattern or textured surface · CPC title

• G03F7/70341

  Details of immersion lithography aspects, e.g. exposure media or control of immersion liquid supply (chemical composition of immersion liquids G03F7/2041) · CPC title