Gallium nitride high-electron mobility transistors with deep implanted p-type layers in silicon carbide substrates for power switching and radio frequency applications and process for making the same

Patent metadata

Field	Value
Publication number	US-10192980-B2
Application number	US-201715424209-A
Country	US
Kind code	B2
Filing date	Feb 3, 2017
Priority date	Jun 24, 2016
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

The disclosure is directed to a high-electron mobility transistor that includes a SiC substrate layer, a GaN buffer layer arranged on the SiC substrate layer, and a p-type material layer having a length parallel to a surface of the SiC substrate layer over which the GaN buffer layer is provided. The p-type material layer is provided in one of the following: the SiC substrate layer and a first layer arranged on the SiC substrate layer. A method of making the high-electron mobility transistor is also disclosed.

First claim

What is claimed is:

1. A high-electron mobility transistor comprising:
a substrate layer;
a buffer layer arranged on the substrate layer;
a p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided; and
a p+ type material layer being arranged on the p-type material layer,
wherein the p-type material layer is provided in one of the following locations: the substrate layer or a first layer arranged on the substrate layer;
wherein the p+ type material layer comprises a doping concentration greater than a doping concentration of the p-type material layer; and
wherein a thickness of the p-type material layer is greater than a thickness of the p+ type material layer.

2. The transistor of claim 1 ,
wherein the p+ type material layer comprises a length parallel to the surface of the substrate layer over which the buffer layer is provided, the length of the p+ type material layer being less than an entire length of the substrate layer parallel to the surface of the substrate layer,
wherein the p-type material layer and the p+ type material layer are provided in one of the following locations: the substrate layer or the first layer arranged on the substrate layer,
wherein the substrate layer comprises SiC, and
wherein the buffer layer comprises at least one of the following: GaN, AlGaN, or AlN.

3. The transistor of claim 2 ,
wherein the p+ type material layer length parallel to the surface of the substrate layer extends at least from a source to at least to an edge of a gate adjacent to a drain; and
wherein the length of the p-type material layer is less than an entire length of the substrate layer.

4. The transistor of claim 1 ,
wherein the length of the p-type material layer is less than an entire length of the substrate layer parallel to the surface of the substrate layer.

5. The transistor of claim 4 ,
wherein the p-type material layer length parallel to a surface of the substrate layer extends at least from a source toward an edge of a gate adjacent a drain; and
wherein the length of the p-type material layer is greater than a length of the p+ type material layer.

6. A high-electron mobility transistor comprising:
a substrate layer;
a buffer layer arranged on the substrate layer;
a p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided; and
a p+ type material layer being arranged on the p-type material layer,
wherein the p+ type material layer comprises a doping concentration greater than a doping concentration of the p-type material layer;
wherein the p-type material layer is provided in the substrate layer;
wherein the p-type material layer comprises aluminum implanted in the substrate layer; and
wherein a thickness of the p-type material layer is greater than a thickness of the p+ type material layer.

7. A high-electron mobility transistor comprising:
a substrate layer;
a buffer layer arranged on the substrate layer;
a p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided; and
a p+ type material layer being arranged on the p-type material layer,
wherein the p-type material layer is provided in one of the following locations: the substrate layer or a first layer arranged on the substrate layer; and
wherein the p+ type material layer comprises a doping concentration greater than a doping concentration of the p-type material layer;
wherein the p+ type material layer comprises a length parallel to the surface of the substrate layer over which the buffer layer is provided, the length of the p+ type material layer being less than an entire length of the substrate layer parallel to the surface of the substrate layer;
wherein the p+ type material layer is provided in the substrate layer;
wherein the p+ type material layer comprises aluminum implanted in the substrate layer; and
wherein a thickness of the p-type material layer is greater than a thickness of the p+ type material layer.

8. The transistor of claim 1 ,
wherein the p-type material layer is provided in the first layer arranged on the substrate layer;
wherein the first layer is SiC and comprises an epitaxial layer;
wherein the p-type material layer comprises aluminum in the epitaxial layer; and
wherein the p+ type material layer comprises a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p+ type material layer being less than an entire length of the substrate layer parallel to the surface of the substrate layer.

9. The transistor of claim 6 ,
wherein the p-type material layer is provided in the substrate layer;
wherein the p-type material layer is configured to have a depth greater than 0.5 μm;
wherein the p+ type material layer comprises a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p+ type material layer being less than an entire length of the substrate layer parallel to the surface of the substrate layer;
wherein the substrate layer comprises SiC; and
wherein the buffer layer comprises at least one of the following: GaN, AlGaN, or AlN.

10. The transistor of claim 7 ,
wherein the p-type material layer extends over the entire length of one of the following: the substrate layer and the first layer arranged on the substrate layer;
wherein the p+ type material layer comprises a length parallel to a surface of the substrate layer over which the buffer layer is provided, the length of the p+ type material layer being less than an entire length of the substrate layer parallel to the surface of the substrate layer;
wherein the substrate layer comprises SiC; and
wherein the buffer layer comprises at least one of the following: GaN, AlGaN, or AlN.

11. A method of making a high-electron mobility transistor comprising:
providing a substrate layer;
providing a buffer layer on the substrate layer;
providing a p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided;
providing a p+ type material layer on the p-type material layer; and
providing the p-type material layer in one of the following locations: the substrate layer or a first layer arranged on the substrate layer,
wherein the p+ type material layer comprises a doping concentration greater than a doping concentration of the p-type material layer,
wherein a thickness of the p-type material layer is greater than a thickness of the p+ type material layer.

12. The method of claim 11 , further comprising:
providing the p+ type material layer further comprises providing the p+ type material layer having a length parallel to a surface of the substrate layer over which the buffer layer is provided such that the length of the p+ type material layer is less than an entire length of the substrate layer parallel to the surface of the substrate layer;
providing the p-type material layer and the p+ type material layer in one of the following locations: the substrate layer or the first layer arranged on the substrate layer; and
the providing the p-type material layer having a length parallel to a surface of the substrate layer over which the buffer layer further comprises implanting the p-type material layer utilizing channeling conditions.

13. The method of claim 12 ,
wherein the p+ type material layer length parallel to the surface of the substrate layer extends at least from a source to at least to an edge of a gate adjacent to the drain.

14. A method of making a high-ele

Assignees

• Cree Inc

Inventors

• Sriram Saptharishi
• Suvorov Alexander
• Hallin Christer

Classifications

• H10P95/408

  of Group III-V semiconductors, e.g. to render them semi-insulating · CPC title

• H10P30/21

  of electrically active species · CPC title

• H10P30/206

  into Group III-V semiconductors · CPC title

• H01L29/42376

  Electricity · mapped topic

• H01L29/7787 Primary

  Electricity · mapped topic