Composite gate dielectric layer applied to group III-V substrate and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10192963-B2
Application number	US-201515539597-A
Country	US
Kind code	B2
Filing date	Jul 16, 2015
Priority date	Jul 16, 2015
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

The present invention discloses a composite gate dielectric layer for a Group III-V substrate and a method for manufacturing the same. The composite gate dielectric layer comprises: an Al x Y 2-x O 3 interface passivation layer formed on the group III-V substrate; and a high dielectric insulating layer formed on the Al x Y 2-x O 3 interface passivation layer, wherein 1.2≤x≤1.9. The composite gate dielectric layer modifies the Al/Y ratio of the Al x Y 2-x O 3 interface passivation layer, changes the average number of atomic coordination in the Al x Y 2-x O 3 interface passivation layer, and decreases the interface state density and boundary trap density of the Group III-V substrate, increases the mobility of the MOS channel. By cooperation of the Al x Y 2-x O 3 interface passivation layer and high dielectric insulation layer, it reduces leakage current and improves tolerance of the dielectric layer on the voltage, and improves the quality of the MOS capacitor of the Group III-V substrate and enhances its reliability.

First claim

We claim:

1. A composite gate dielectric layer for a Group III-V substrate, comprising:
an Al x Y 2-x O 3 interface passivation layer formed on the group III-V substrate by thermally treating an Al 2 O m passivation layer formed on the group III-V substrate and a Y 2 O n strengthening layer formed on the Al 2 O m passivation layer in situ to mix the Al 2 O m passivation layer and the Y 2 O n strengthening layer; and
a high-k dielectric insulating layer formed on the Al x Y 2-x O 3 interface passivation layer, wherein 1.2≤x≤1.9.

2. The composite gate dielectric layer for a Group III-V substrate according to claim 1 , wherein the group III-V substrate includes a GaAs substrate, an InP substrate, a GaSb substrate, an InAs substrate or an InGaAs substrate and an epitaxial wafer thereof, the doping concentration of which is equal to or more than 1×10 15 cm −3 and equal to or less than 5×10 17 cm −3 .

3. The composite gate dielectric layer for a Group III-V substrate according to claim 1 , wherein the Al x Y 2-x O 3 interface passivation layer has a thickness of 0.4 nm or more and 4 nm or less.

4. The composite gate dielectric layer for a Group III-V substrate according to claim 1 , wherein the high-k dielectric insulating layer includes HfO 2 , ZrO 2 , La 2 O 3 or Y 2 O 3 , and a ternary or plural compound obtained by mixing the above mentioned four materials, wherein the high-k dielectric insulating layer has a thickness of 0 nm or more and less than or equal to 4 nm.

5. A method for manufacturing a composite gate dielectric layer for a group III-V substrate, comprising the following steps of:
Step 1: cleaning the group III-V substrate, growing an Al 2 O m passivation layer on the group III-V substrate, wherein 2.5≤m≤3;
Step 2: growing a Y 2 O n strengthening layer on the Al 2 O m passivation layer, wherein 2.5≤n≤3;
Step 3: thermally treating the Al 2 O m passivation layer and the Y 2 O n strengthening layer in situ to mix the Al 2 O m passivation layer and the Y 2 O n strengthening layer to obtain an interface passivation layer of Al x Y 2-x O 3 , wherein 1.2≤x≤1.9; and
Step 4: growing a high-k dielectric insulating layer on the Al x Y 2-x O 3 interface passivation layer.

6. The method according to claim 5 , wherein the step 1 of growing the Al 2 O m passivation layer on the group III-V substrate comprises growing the Al 2 O m passivation layer with a thickness of d 1 _ on the group III-V substrate by atomic layer deposition at a temperature of 200° C. to 400° C., wherein 0.2 nm≤d 1 ≤3.8 nm.

7. The method according to claim 6 , wherein the method regulates an oxygen content in the Al 2 O m passivation layer by adjusting the temperature of atomic layer deposition ranging from 200° C. to 400° C., wherein at 200° C., it tends to form a Al 2 O m passivation layer with a low oxygen content, m=2.5; at 400° C., it tends to form a Al 2 O m passivation layer with a high oxygen content, m=3, wherein the lower oxygen content in the Al 2 O m passivation layer improves a flexibility of the Al—O tetrahedron mesh structure in the Al 2 O m passivation layer, and enhances a characteristic of rotation of the Al—O tetrahedron in the Al 2 O m passivation layer, so as to passivize the defects on the surface of the group III-V substrate, and the higher oxygen content in the Al 2 O m passivation layer decreases the leakage current of the composite gate dielectric layer and improve the reliability.

8. The method according to claim 6 , wherein the step 2 of growing the Y 2 O n strengthening layer on the Al 2 O m passivation layer comprises growing the Y 2 O n strengthening layer with a thickness of d 2 _ on the Al 2 O m passivation layer by atomic layer deposition at a temperature of 200° C. to 400° C., wherein 0.4 nm≤d 1 +d 2 ≤4 nm.

9. The method according to claim 8 , wherein the method regulates an oxygen content in the Y 2 O n strengthening layer by adjusting the temperature of the atomic layer deposition ranging from 200° C. to 400° C., wherein at 200° C., it tends to form a Y 2 O n strengthening layer with a low oxygen content, n=2.5; at 400° C., it tends to form a Y 2 O n strengthening layer with a high oxygen content, n=3.

10. The method according to claim 5 , wherein the step 3 of thermally treating the Al 2 O m passivation layer and the Y 2 O n strengthening layer in situ is implemented by thermally treating the Al 2 O m passivation layer and the Y 2 O n strengthening layer in an atomic layer deposition apparatus at a temperature ranging from 200° C. to 400° C.

11. The method according to claim 10 , wherein the Al 0 O m passivation layer and the Y 2 O n strengthening layer are mixed according to a certain mixing ratio by adjusting the temperature for the thermal treating in situ, and the mixing ratio is determined by a ratio of d1:d2 of the thickness d 1 of the Al 2 O m passivation layer and the thickness d 2 of the Y 2 O n strengthening layer, wherein 19:1≤d 1 :d 2 ≤1:19;
the Al x Y 2-x O 3 interface passivation layer is obtained by mixing the Al 2 O m passivation layer and Y 2 O n strengthening layer to implement an average coordination number of the Al x Y 2-x O 3 interface passivation layer ranging from 2.8 to 4.2, and in turn to meet the requirement of interfacial defect density and reliability of various devices; wherein the average coordination number of 2.8 is obtained under a condition in which d 1 :d 2 =19:1, m=3 and n=3; and the average coordination number of is 4.2 is obtained under a condition in which d1:d2=1:19, m=2.5 and n=2.5.

12. The method according to claim 11 , wherein the Al x Y 2-x O 3 interface passivation layer, 1.2≤x≤1.9 is a referable result of the interface passivation layer, and the average coordination number of the Al x Y 2-x O 3 interface passivation layer ranges from 3.28 to 2.86, in which the average coordination number is 3.28 at x=1.2 and 2.86 at x=1.9.

13. The method according to claim 5 , wherein the step 4 of growing the high-k dielectric insulating layer on the Al x Y 2-x O 3 interface passivation layer is implemented by utilizing atomic layer deposition to deposit a high dielectric insulating layer with a thickness of equal to or more than 0 nm and less than or equal to 4 nm on the Al x Y 2-x O 3 interface passivation layer at a temperature ranging from of 200° C. to 400° C.

Assignees

• Inst Of Microelectronics Chinese Academy Of Science
• Inst Of Microelectronics Cas

Inventors

• Wang Shengkai
• Liu Honggang
• Sun Bing
• Chang Hudong

Classifications

• H10P14/69396

  the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium · CPC title

• H10P14/69391

  the material containing aluminium, e.g. Al2O3 · CPC title

• H10P14/6544

  to change the morphology of the insulating materials, e.g. transformation of an amorphous layer into a crystalline layer · CPC title

• H10P14/6504

  In-situ cleaning · CPC title

• H10P14/6339

  deposition by cyclic CVD, e.g. ALD, ALE or pulsed CVD · CPC title