Semiconductor devices including low-k metal gate isolation and methods of fabrication thereof
US-12009259-B2 · Jun 11, 2024 · US
Production method of semiconductor device, semiconductor wafer, and semiconductor device
US9214522B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9214522-B2 |
| Application number | US-201314134325-A |
| Country | US |
| Kind code | B2 |
| Filing date | Dec 19, 2013 |
| Priority date | Jan 18, 2013 |
| Publication date | Dec 15, 2015 |
| Grant date | Dec 15, 2015 |
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- Title
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Abstract
Official abstract text for this publication.
A semiconductor wafer, includes: a plurality of element regions; a surface electrode that is disposed in each of the plurality of element regions; an insulating layer that is disposed in each of the plurality of element regions and of which height from a front side surface of the semiconductor wafer is higher than that of the surface electrode in a periphery of the surface electrode; and a dicing line groove that is formed in a front side surface of the semiconductor wafer, that surrounds the surface electrode with the insulating layer therebetween, of which height from the front side surface of the semiconductor wafer is lower than that of the insulating layer, and that extends to a perimeter of the semiconductor wafer; in which the insulating layer is formed with a communication passage that extends from a side of the surface electrode to the dicing line groove.
First claim
Opening claim text (preview).
What is claimed is: 1. A production method of a semiconductor device, comprising: forming, in each of a plurality of element regions disposed in a semiconductor wafer, a surface electrode and an insulating layer in a periphery of the surface electrode of which height from a front side surface of the semiconductor wafer is higher than that of the surface electrode; forming, in the front side surface of the semiconductor wafer, a dicing line groove that surrounds the surface elect…
Assignees
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Classifications
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
- H10D64/118Primary
Electricity · mapped topic
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Frequently asked questions
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- What does patent US9214522B2 cover?
- A semiconductor wafer, includes: a plurality of element regions; a surface electrode that is disposed in each of the plurality of element regions; an insulating layer that is disposed in each of the plurality of element regions and of which height from a front side surface of the semiconductor wafer is higher than that of the surface electrode in a periphery of the surface electrode; and a dici…
- Who is the assignee on this patent?
- Kato Kunihito, Onishi Toru, Toyota Motor Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10D64/118. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 15 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).