Transistor array panel and method of manufacturing thereof

Patent metadata

Field	Value
Publication number	US-10192890-B2
Application number	US-201715454337-A
Country	US
Kind code	B2
Filing date	Mar 9, 2017
Priority date	May 18, 2016
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

A transistor display panel including: a substrate; a gate electrode disposed on the substrate; a semiconductor that overlaps the gate electrode; an upper electrode disposed on the semiconductor; a source connection member and a drain connection member disposed on the same layer as the upper electrode and respectively connected with the semiconductor; a source electrode connected with the source connection member and the upper electrode; and a drain electrode connected with the drain connection member.

First claim

What is claimed is:

1. A transistor display panel comprising:
a substrate; and
a transistor disposed on the substrate,
wherein the transistor comprises:
a gate electrode disposed on the substrate;
a semiconductor that overlaps the gate electrode;
an upper electrode disposed on the semiconductor and overlapping the gate electrode;
a source connection member and a drain connection member disposed on the same layer as the upper electrode and respectively connected with the semiconductor;
a source electrode connected with the source connection member and the upper electrode; and
a drain electrode connected with the drain connection member.

2. The transistor display panel of claim 1 , wherein the upper electrode overlaps the semiconductor.

3. The transistor display panel of claim 2 , further comprising:
a first insulation layer disposed between the gate electrode and the semiconductor; and
a second insulation layer disposed between the semiconductor and the upper electrode.

4. The transistor display panel of claim 3 , wherein:
the second insulation layer comprises a first opening and a second opening that overlap the semiconductor and are disposed apart from each other; and
the source connection member and the drain connection member are connected with the semiconductor through the first opening and the second opening.

5. The transistor display panel of claim 4 , further comprising a third insulation layer that covers the upper electrode, the drain connection member, and the source connection member.

6. The transistor display panel of claim 5 , wherein:
the third insulation layer comprises a first contact hole, a second contact hole, and a third contact hole;
the first contact hole and the second contact hole respectively overlap the source connection member and the drain connection member;
the source electrode is connected with the source connection member and the upper electrode through the first contact hole and the third contact hole; and
the drain electrode is connected with the drain connection member through the second contact hole.

7. The transistor display panel of claim 1 , further comprising a pixel electrode that is electrically connected with the source electrode.

8. The transistor display panel of claim 1 , wherein the semiconductor comprises an oxide semiconductor.

9. The transistor display panel of claim 6 , further comprising:
a switching semiconductor spaced apart from the semiconductor and disposed on the same layer as the semiconductor; and
a gate line disposed on the switching semiconductor, disposed on the same layer as the upper electrode, and transmitting a gate signal,
wherein a portion of the gate line overlaps the switching semiconductor.

10. The transistor display panel of claim 9 , further comprising a connection electrode disposed on the same layer as the source electrode and connecting the switching semiconductor and the gate electrode.

11. The transistor display panel of claim 10 , wherein:
the third insulation layer has a fourth contact hole overlapping the gate electrode, and a fifth contact hole overlapping the connection electrode; and
one end portion of the connection electrode is connected to the gate electrode through the fourth contact hole, and the other end portion of the connection electrode is connected to the switching semiconductor through the fifth contact hole.

12. The transistor display panel of claim 10 , wherein one end portion of the connection electrode overlaps the gate electrode in a plane view, and the other end portion of the connection electrode overlaps the switching semiconductor in a plane view.

13. The transistor display panel of claim 10 , wherein the switching semiconductor comprises an oxide semiconductor.

14. The transistor display panel of claim 10 , further comprising a data line disposed on the same layer as the connection electrode,
wherein a portion of the data line overlaps the switching semiconductor.

15. The transistor display panel of claim 14 , wherein the portion of the data line is connected to the switching semiconductor.

16. A method of manufacturing a transistor display panel, comprising forming a transistor on a substrate,
wherein the forming of the transistor comprises:
forming a gate electrode on the substrate;
forming a semiconductor that overlaps the gate electrode;
forming an upper electrode, a source connection member, and a drain connection member, wherein the upper electrode overlaps the semiconductor and the gate electrode, and the source connection member and the drain connection member are connected with the semiconductor; and
forming a source electrode that is connected with the upper electrode and the source connection member and a drain electrode that is connected with the drain connection member.

17. The method of claim 16 , wherein the upper electrode is formed on the semiconductor.

18. The method of claim 17 , further comprising:
forming a first insulation layer that covers the gate electrode;
forming a second insulation layer that covers the semiconductor; and
forming a first opening and a second opening in the second insulation layer, the first opening and the second opening overlapping the semiconductor,
wherein the source connection member and the drain connection member are connected with the semiconductor respectively through the first opening and the second opening.

19. The method of claim 18 , further comprising forming a third insulation layer that covers the upper electrode, the drain connection member, and the source connection member.

20. The method of claim 19 , further comprising forming a first contact hole, a second contact hole, and a third contact hole, wherein:
the first contact hole and the second contact hole respectively overlap the source connection member and the drain connection member;
the third contact hole overlaps the upper electrode; and
the source electrode is connected with the source connection member and the upper electrode through the first contact hole and the third contact hole, and the drain electrode is connected with the drain connection member through the second contact hole.

Assignees

• Samsung Display Co Ltd
• Samsung Display Co Ltd

Inventors

• Park Jae-Hyun

Classifications

• H01L27/3262

  Electricity · mapped topic

• H01L27/1259

  Electricity · mapped topic

• H01L29/78648

  Electricity · mapped topic

• H01L29/42356

  Electricity · mapped topic

• H01L29/7869

  Electricity · mapped topic