Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound

Patent metadata

Field	Value
Publication number	US-10192801-B2
Application number	US-201213424484-A
Country	US
Kind code	B2
Filing date	Mar 20, 2012
Priority date	Dec 8, 2008
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

A semiconductor device is made with a conductive via formed through a top-side of the substrate. The conductive via extends vertically through less than a thickness of the substrate. An integrated passive device (IPD) is formed over the substrate. A plurality of first conductive pillars is formed over the first IPD. A first semiconductor die is mounted over the substrate. An encapsulant is formed around the first conductive pillars and first semiconductor die. A second IPD is formed over the encapsulant. An interconnect structure is formed over the second IPD. The interconnect structure operates as a heat sink. A portion of a back-side of the substrate is removed to expose the first conductive via. A second semiconductor die is mounted to the back-side of the substrate. The second semiconductor die is electrically connected to the first IPD and first semiconductor die through the conductive via.

First claim

What is claimed:

1. A semiconductor device, comprising:
a semiconductor substrate;
a first semiconductor die disposed over a first surface of the semiconductor substrate;
a capacitor formed over the first surface of the semiconductor substrate and laterally offset from the first semiconductor die, the capacitor including,
(a) a first conductive layer formed over the first surface of the semiconductor substrate,
(b) an insulating layer formed over the first conductive layer, and
(c) a second conductive layer formed over the insulating layer;

an encapsulant deposited around the first semiconductor die and over the capacitor;
a vertical interconnect structure formed through the encapsulant; and
a third conductive layer formed over a surface of the encapsulant opposite the capacitor, wherein the third conductive layer is in physical contact with the vertical interconnect structure and a portion of the third conductive layer is wound to form an inductor.

2. The semiconductor device of claim 1 , further including a resistor formed over the first conductive layer.

3. The semiconductor device of claim 1 , wherein a thickness of the encapsulant over the capacitor is at least 50 micrometers.

4. The semiconductor device of claim 1 , further including a second semiconductor die disposed over a second surface of the semiconductor substrate opposite the first surface of the semiconductor substrate.

5. The semiconductor device of claim 1 , further including a heat sink disposed over the first semiconductor die.

6. The semiconductor device of claim 1 , further including a second semiconductor die disposed over the first semiconductor die.

7. A semiconductor device, comprising:
a semiconductor substrate;
a conductive via formed through the semiconductor substrate;
a first semiconductor die disposed over a first surface of the semiconductor substrate;
a first integrated passive device (IPD) formed over the first surface of the semiconductor substrate and laterally offset from the first semiconductor die;
an encapsulant deposited in contact with the first semiconductor die and first IPD; and
a second IPD formed over a surface of the encapsulant opposite the first IPD and laterally offset from the first semiconductor die, wherein the second IPD includes a first conductive layer formed over the surface of the encapsulant and wound to form an inductor.

8. The semiconductor device of claim 7 , wherein the first IPD includes a capacitor or resistor.

9. The semiconductor device of claim 7 , further including a heat sink disposed over the first semiconductor die.

10. The semiconductor device of claim 7 , further including an interconnect structure formed through the encapsulant, wherein the first conductive layer formed over the surface of the encapsulant contacts the interconnect structure.

11. The semiconductor device of claim 7 , further including a second semiconductor die disposed over the first semiconductor die.

12. A semiconductor device, comprising:
a substrate including a semiconductor material;
a first semiconductor die disposed over a first surface of the substrate;
a first integrated passive device (IPD) disposed over the first surface of the substrate and laterally offset from the first semiconductor die;
an encapsulant deposited over the first IPD; and
a second IPD formed over a surface of the encapsulant opposite the first IPD and laterally offset from the first semiconductor die, wherein the second IPD includes a first conductive layer formed over the surface of the encapsulant opposite the first IPD and wound to form an inductor.

13. The semiconductor device of claim 12 , further including a conductive via formed through the substrate.

14. The semiconductor device of claim 12 , further including a second semiconductor die disposed over the first semiconductor die.

15. The semiconductor device of claim 12 , wherein the first IPD includes a capacitor or resistor.

16. The semiconductor device of claim 12 , wherein the first IPD includes:
a second conductive layer;
an insulating layer formed over the second conductive layer; and
a third conductive layer formed over the insulating layer.

17. The semiconductor device of claim 12 , further including an interconnect structure formed through the encapsulant, wherein the first conductive layer contacts the interconnect structure.

18. A semiconductor device, comprising:
a substrate including a semiconductor material;
a first semiconductor die disposed over a surface of the substrate;
an integrated passive device (IPD) disposed over the surface of the substrate laterally offset from the first semiconductor die;
an encapsulant deposited over the IPD;
an interconnect structure formed through the encapsulant; and
a first conductive layer wound to form an inductor over a surface of the encapsulant opposite the IPD and in contact with the interconnect structure.

19. The semiconductor device of claim 18 , further including a second semiconductor die disposed over the first semiconductor die.

20. The semiconductor device of claim 18 , wherein the IPD includes a capacitor or resistor.

21. The semiconductor device of claim 18 , wherein the IPD includes:
a second conductive layer formed over the surface of the substrate;
an insulating layer formed over the second conductive layer; and
a third conductive layer formed over the insulating layer.

22. The semiconductor device of claim 18 , further including an insulating layer formed over the encapsulant, wherein the first conductive layer is formed over the insulating layer.

23. The semiconductor device of claim 7 , wherein the first IPD includes:
a second conductive layer formed over the first surface of the semiconductor substrate;
an insulating layer formed over the second conductive layer; and
a third conductive layer formed over the insulating layer.

24. The semiconductor device of claim 1 , further including a plurality of conductive vias formed through the semiconductor substrate.

25. The semiconductor device of claim 7 , further including a second semiconductor die disposed over a second surface of the semiconductor substrate opposite the first surface of the semiconductor substrate.

26. The semiconductor device of claim 12 , further including a second conductive layer formed over the second IPD.

Assignees

• Lin Yaojian
• Fang Jianmin
• Chen Kang
• Cao Haijing
• Stats Chippac Pte Ltd

Inventors

• Lin Yaojian
• Fang Jianmin
• Chen Kang
• Cao Haijing

Classifications

• H10W20/0245

  comprising use of blind vias during the manufacture · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title