GOA drive unit and drive circuit

Patent metadata

Field	Value
Publication number	US-10192505-B2
Application number	US-201615324700-A
Country	US
Kind code	B2
Filing date	Nov 29, 2016
Priority date	Aug 31, 2016
Publication date	Jan 29, 2019
Grant date	Jan 29, 2019

Abstract

Disclosed is a GOA drive unit and drive circuit. The GOA drive unit includes a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down holding unit, a bootstrap capacitor, and a pull-down transistor of an adjacent row. The pull-down transistor of an adjacent row is configured to pull down and hold a line scan signal of an adjacent row corresponding to a previous scanning sequence at a low level when a scan control signal and a line scan signal of a current row are pulled down and held at low levels by the pull-down holding unit. The GOA drive unit can improve the self-repairing ability of the GOA drive circuit.

First claim

The invention claimed is:

1. A GOA drive unit, comprising: a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down holding unit, and a bootstrap capacitor,
wherein the pull-up unit is configured to transform a scanning clock signal inputted to a line scan signal outputted, the pull-up control unit is linked to the pull-up unit and used to provide a scan control signal to the pull-up unit for controlling a time for turning on the pull-up unit, the pull-down unit is linked to the pull-up unit and used for controlling a turning-off operation to the line scan signal by an effective line scan signal of a next row, the pull-down holding unit is linked to the pull-up control unit and the pull-up unit and used to pull down and hold the scan control signal and the line scan signal at a low level during scanning periods of other rows, and the bootstrap capacitor is linked to the pull-up unit and used to ensure a reliable turned-on of the pull-up unit and a reliable output of the line scan signal;
wherein the GOA drive unit further comprises:
a pull-down transistor of an adjacent row, which is configured to pull down and hold a line scan signal of an adjacent row corresponding to a previous scanning timing at a low level when a scan control signal and a line scan signal of a current row are pulled down and held at low levels by the pull-down holding unit;
wherein the pull-down holding unit comprises a first pull-down transistor for pulling down and holding the scan control signal of the current row at a low level, and a second pull-down transistor for pulling down and holding the line scan signal of the current row at a low level,
wherein drains of the first pull-down transistor and the second pull-down transistor are respectively connected to the scan control signal and the line scan signal,
wherein a drain of the pull-down transistor of an adjacent row is connected to the line scan signal of an adjacent row corresponding to a previous scanning timing, and a gate thereof is coupled to gates of the first pull-down transistor and the second pull-down transistor, and
wherein sources of the first pull-down transistor, the second pull-down transistor and the pull-down transistor of an adjacent row are all coupled to a DC pull-down voltage.

2. The GOA drive unit according to claim 1 ,
wherein the pull-down holding unit further comprises:
a third pull-down transistor, a gate and a drain thereof being coupled together to receive a pull-down clock signal;
a fourth pull-down transistor, a gate and a drain thereof being respectively coupled to a source and a drain of the third pull-down transistor;
a fifth pull-down transistor and a sixth pull-down transistor,
wherein drains of the fifth pull-down transistor and the sixth pull-down transistor are respectively coupled to a gate and a source of the fourth pull-down transistor, sources thereof are coupled to the DC pull-down voltage, and gates thereof are coupled together to receive the scan control signal, and
wherein a drain of the sixth pull-down transistor is coupled to a coupled node of gates of the first pull-down transistor, the second pull-down transistor and the pull-down transistor of an adjacent row.

3. The GOA drive unit according to claim 2 , wherein the pull-down clock signal and a scanning clock signal of the GOA drive unit of the current row are equal in frequency but opposite in phase.

4. The GOA drive unit according to claim 1 , wherein the GOA drive unit further comprises a pass-down unit, which comprises a pass-down transistor,
wherein a gate of the pass-down transistor is connected to the scan control signal, a drain thereof is connected to a scanning clock signal of the GOA drive unit, and a source thereof is configured to generate a pass-down signal applied to a next-stage GOA drive unit.

5. A GOA drive unit, comprising: a pull-up unit, a pull-up control unit, a pull-down unit, a pull-down holding unit, and a bootstrap capacitor,
wherein the pull-up unit is configured to transform a scanning clock signal inputted to a line scan signal outputted, the pull-up control unit is linked to the pull-up unit and used to provide a scan control signal to the pull-up unit for controlling a time for turning on the pull-up unit, the pull-down unit is linked to the pull-up unit and used for controlling a turning-off operation to the line scan signal by an effective line scan signal of a next row, the pull-down holding unit is linked to the pull-up control unit and the pull-up unit and used to pull down and hold the scan control signal and the line scan signal at a low level during scanning periods of other rows, and the bootstrap capacitor is linked to the pull-up unit and used to ensure a reliable turned-on of the pull-up unit and a reliable output of the line scan signal;
wherein the GOA drive unit further comprises:
a pull-down transistor of an adjacent row, which is configured to pull down and hold a line scan signal of an adjacent row corresponding to a previous scanning timing at a low level when a scan control signal and a line scan signal of a current row are pulled down and held at low levels by the pull-down holding unit;
wherein the pull-down holding unit comprises a circuit with a mirrored structure, which comprises:
a first pull-down transistor and a third pull-down transistor used for pulling down and holding the scan control signal of the current row at a low level, and a second pull-down transistor and a fourth pull-down transistor used for pulling down and holding the line scan signal of the current row at a low level,
wherein the pull-down transistor of an adjacent row comprises a first pull-down transistor of an adjacent row and a second pull-down transistor of an adjacent row,
wherein drains of the first pull-down transistor of an adjacent row and the second pull-down transistor of an adjacent row are both connected to the line scan signal of an adjacent row corresponding to a previous scanning timing,
wherein a gate and a source of the first pull-down transistor of an adjacent row are respectively coupled to gates and sources of the first pull-down transistor and the second pull-down transistor, and
wherein a gate and a source of the second pull-down transistor of an adjacent row are respectively coupled to gates and sources of the third pull-down transistor and the fourth pull-down transistor, and
wherein a source of each of the pull-down transistors is coupled to a DC pull-down voltage.

6. The GOA drive unit according to claim 5 ,
wherein the pull-down holding unit further comprises a first alternate control circuit and a second alternate control circuit, which are configured to be mirrored with each other,
wherein the first alternate control circuit comprises:
a fifth pull-down transistor, a gate and a drain thereof being coupled together to receive a first alternate control signal;
a sixth pull-down transistor, a gate and a drain thereof being respectively coupled to a source and a drain of the fifth pull-down transistor;
a seventh pull-down transistor and an eighth pull-down transistor, wherein drains of the seventh pull-down transistor and the eighth pull-down transistor are respectively coupled to a gate and a source of the sixth pull-down transistor, sources thereof are coupled to the DC pull-down voltage, and gates thereof are coupled together to receive the scan control signal, and wherein a drain of the eighth pull-down transistor is coupled to a coupled node of gates of the first pull-down transistor, the second pull-down transistor and the first pull-down transistor of an adjacent row; and
wherein the second alternate control circuit is configured with a mirrored structure corresponding to the first alternate control circuit, and is controlled by a second alternate control signal,
wherei

Assignees

• Shenzhen China Star Optoelect

Inventors

• Zeng Mian

Classifications

• G09G3/3677 Primary

  suitable for active matrices only · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title

• G02F1/13

  based on liquid crystals, e.g. single liquid crystal display cells · CPC title

• G09G2310/06

  Details of flat display driving waveforms · CPC title

• G02F1/13306

  Circuit arrangements or driving methods for the control of single liquid crystal cells (G02F1/132, G02F1/133382 take precedence) · CPC title