Liquid crystal display device and GOA circuit

Patent metadata

Field	Value
Publication number	US-9972261-B2
Application number	US-201614907825-A
Country	US
Kind code	B2
Filing date	Jan 11, 2016
Priority date	Dec 24, 2015
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

A GOA (Gate driver On Array) for an LCD (Liquid Crystal Display) device is disclosed herein. The LCD device comprises a plurality of scanning lines. The GOA circuit comprises a plurality of GOA units, which are cascaded with each other as a plurality of level GOA units. The (n)th level GOA unit comprises a clock circuit, a pull-down circuit, a bootstrap capacitor circuit, a pull-up circuit, and a pull-down sustain circuit, to improve the color shift issue of a Tri-gate.

First claim

What is claimed is:

1. A GOA (Gate driver On Array) circuit for an LCD (Liquid Crystal Display) device, the LCD device comprises a plurality of scanning lines, the GOA circuit comprising:
a plurality of GOA units, being cascaded with each other as multiple levels of GOA units, the (n)th level GOA unit comprising:
a clock circuit for receiving an (m)th level clock signal of a plurality of level clock signals, and being connected with an (n)th level starting signal and an (n)th level scanning line of the scanning lines;
a pull-down circuit being connected with a gate signal point, the (n)th level scanning line, an (n+2)nd level scanning line of the plurality of scanning lines, an (n+2)nd level starting signal and a constant voltage source;
a bootstrap capacitor circuit for connecting with the gate signal point and the constant voltage source;
a pull-up circuit for connecting with the gate signal point, an (n−2)nd level scanning line of the plurality of scanning lines, and an (n−2)nd level starting signal;
a pull-down sustain circuit for connecting with the gate signal point, the constant voltage source, and the (n)th level scanning line;
wherein the numeral m and the numeral n are integers, the clock circuit comprises a first transistor, a control terminal of the first transistor is connected with the gate signal point, an input terminal of the first transistor receives the (m)th level clock signal, an output terminal of the first transistor is connected with the (n)th level scanning line, the pull-down circuit comprises a third transistor, a control terminal of the third transistor is connected with the (n+2)nd level scanning line and the (n+2)nd level starting signal, an input terminal of the third transistor is connected with the constant voltage source, an output terminal of the third transistor is connected with the (n)th level scanning line;
wherein the pull-up circuit comprises:
a fifth transistor, a control terminal of the fifth transistor is directly connected with the (n−2)nd level scanning line and the (n−2)nd level starting signal, an input terminal of the fifth transistor is connected with the control terminal of the fifth transistor, an output terminal of the fifth transistor is connected with the gate signal point; wherein the pull-down sustain circuit comprises a first pull-down sustain circuit and a second pull-down sustain circuit;
wherein the first pull-down sustain circuit comprises:
a sixth transistor, an input terminal of the sixth transistor connects with the constant voltage source, an output terminal of the sixth transistor connects with the gate signal point;
a seventh transistor, a control terminal of the seventh transistor receives a first low-frequency signal, an output terminal of the seventh transistor connects with the control terminal of the seventh transistor; and
an eighth transistor, a control terminal of the eighth transistor connects with the gate signal point, an input terminal of the eighth transistor connects with the constant voltage source;
the second pull-down sustain circuit comprises:
a ninth transistor, an input terminal of the ninth transistor connects with the constant voltage source, an output terminal of the ninth transistor connects with the gate signal point;
a tenth transistor, a control terminal of the tenth transistor receives a second low-frequency signal, an output terminal of the tenth transistor connects with the control terminal of the tenth transistor; and
an eleventh transistor, a control terminal of the eleventh transistor connects with the gate signal point, an input terminal of the eleventh transistor connects with the constant voltage source;
wherein the first low-frequency signal and the second frequency signal exchange directions every 100 frames.

2. The GOA circuit for the LCD device according to claim 1 , wherein the clock circuit comprises:
a second transistor, a control terminal of the second transistor connects with the gate signal point, an input terminal of the second transistor connects with the input terminal of the first transistor, an output terminal of the second transistor connects with the (n)th level starting signal.

3. The GOA circuit for the LCD device according to claim 1 , wherein each of the plurality of level clock signals has the same duty cycle.

4. The GOA circuit for the LCD device according to claim 1 , wherein the pull-down circuit comprises:
a fourth transistor, a control terminal of the fourth transistor connects with the (n+2)nd level scanning line and the (n+2)nd level starting signal, an input terminal of the fourth transistor connects with the constant voltage source, an output terminal of the fourth transistor connects with the gate signal point.

5. The GOA circuit for the LCD device according to claim 1 , wherein the bootstrap capacitor circuit comprises:
a first capacitor having two terminals which are connected with the gate signal point and the (n)th level scanning line.

6. The GOA circuit for the LCD device according to claim 1 , wherein the first low-frequency signal and the second frequency signal are reversed.

7. A GOA (Gate driver On Array) circuit for an LCD (Liquid Crystal Display) device, the LCD device comprises a plurality of scanning lines, the GOA circuit comprising:
a plurality of GOA units, being cascaded to each other as multiple levels of GOA units, the nth level GOA unit comprising:
a clock circuit for receiving an (m)th level clock signal of a plurality of level clock signals, and being connected with an nth level starting signal and an nth level scanning line of the scanning lines;
a pull-down circuit being connected with a gate signal point, the (n)th level scanning line, an (n+2)nd level scanning line of the plurality of scanning lines, an (n+2)nd level starting signal and a constant voltage source;
a bootstrap capacitor circuit for connecting with the gate signal point and the constant voltage source;
a pull-up circuit for connecting with the gate signal point, an (n−2)nd level scanning line of the plurality of scanning lines, and an (n−2)nd level starting signal;
a pull-down sustain circuit for connecting with the gate signal point, the constant voltage source, and the (n)th level scanning line;
wherein the numeral m and the numeral n are integers;
wherein the pull-up circuit comprises:
a fifth transistor, a control terminal of the fifth transistor is directly connected with the (n−2)nd level scanning line and the (n−2)nd level starting signal, an input terminal of the fifth transistor is connected with the control terminal of the fifth transistor, an output terminal of the fifth transistor is connected with the gate signal point;
wherein the pull-down sustain circuit comprises a first pull-down sustain circuit and a second pull-down sustain circuit;
the first pull-down sustain circuit comprises:
a sixth transistor, an input terminal of the sixth transistor connects with the constant voltage source, an output terminal of the sixth transistor connects with the gate signal point;
a seventh transistor, a control terminal of the seventh transistor receives a first low-frequency signal, an output terminal of the seventh transistor connects with the control terminal of the seventh transistor; and
an eighth transistor, a control terminal of the eighth transistor connects with the gate signal point, an input terminal of the eighth transistor connects with the constant voltage source;
the second pull-down sustain circuit comprises:
a ninth transistor, an input terminal of the ninth transistor connects with the constant voltage source, an output terminal of the ninth transistor connects with the gate signal point;
a tenth transistor, a control terminal of the tenth transistor receives a second low-frequency signal, an o

Assignees

• Shenzhen China Star Optoelect

Inventors

• Wang Xiaoxiao
• Du Peng

Classifications

• G09G2300/0452

  Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components · CPC title

• G09G2310/0251

  Precharge or discharge of pixel before applying new pixel voltage · CPC title

• G09G3/3648 Primary

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title

• G09G2320/0242

  Compensation of deficiencies in the appearance of colours · CPC title

• G09G2230/00

  Details of flat display driving waveforms · CPC title