Regenerative differential detector

Patent metadata

Field	Value
Publication number	US-10187101-B2
Application number	US-201615384305-A
Country	US
Kind code	B2
Filing date	Dec 19, 2016
Priority date	Dec 19, 2016
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

A regenerative differential receiver includes, for example, a transformer arranged to receive a modulated differential signal. A first detector is arranged to source a first output current for indicating a first power level in response to falling voltage of a first line of the modulated differential signal. A second detector is arranged to sink a second output current for indicating a second power level in response to rising voltage of a first line of the modulated differential signal. A cross-coupled latch is arranged to latch a state in response to the first and second power levels. The cross-coupled latch provides, for example, weak non-linear regeneration for increasing receiver gain and maximum operating frequencies.

First claim

What is claimed is:

1. A circuit, comprising:
first and second lines to receive a modulated differential signal;
a first square-law detector, coupled to the first and second lines, to source a first output current in response to a voltage of the first line and a voltage of the second line, the first output current having a first direction, the voltage of the first line having a first polarity, and the voltage of the second line having a second polarity opposite the first polarity;
a second square-law detector, coupled to the first and second lines, to sink a second output current in response to the voltage of the first line and the voltage of the second line, the second output current having a second direction opposite the first direction; and
a cross-coupled latch to latch a state in response to the first and second output currents.

2. The circuit of claim 1 , wherein:
the first square-law detector includes: a first PMOS transistor having a gate coupled to the voltage of the first line; and a second PMOS transistor having a gate coupled to the voltage of the second line; wherein a drain of the first PMOS transistor is coupled to a drain of the second PMOS transistor; and
the second square-law detector includes: a first NMOS transistor having a gate coupled to the voltage of the first line; and a second NMOS transistor having a gate coupled to the voltage of the second line; wherein a drain of the first NMOS transistor is coupled to a drain of the second NMOS transistor.

3. The circuit of claim 2 , further comprising: an NMOS load transistor coupled to sink the first output current from the drains of the first and second PMOS transistors; and a PMOS load transistor coupled to source the second output current from the drains of the first and second NMOS transistors.

4. The circuit of claim 3 , wherein: the cross-coupled latch includes first and second inverters; an output of the first inverter is coupled to an input of the second inverter; and an output of the second inverter is coupled to an input of the first inverter.

5. The circuit of claim 4 , wherein: the input of the first inverter is coupled to the drains of the first and second PMOS transistors; and the input of the second inverter is coupled to the drains of the first and second NMOS transistors.

6. The circuit of claim 5 , further comprising a differential voltage output having first and second outputs to indicate an envelope of information encoded in the modulated differential signal, the first output being coupled to the drains of the first and second PMOS transistors, and the second output being coupled to the drains of the first and second NMOS transistors.

7. The circuit of claim 2 , wherein the first and second PMOS transistors and the first and second NMOS transistors are biased in accordance with an active or subthreshold mode of transconductance.

8. The circuit of claim 1 , further comprising a device to galvanically isolate a transmitter from the first and second square-law detectors, wherein the first and second lines are coupled through the device to receive the modulated differential signal from the transmitter.

9. The circuit of claim 8 , wherein: the device is a transformer; a secondary coil of the transformer is coupled to the first and second lines; and a primary coil of the transformer is coupled to the transmitter.

10. The circuit of claim 9 , wherein the first square-law detector is coupled through a first coupling network to the first and second lines, and the second square-law detector is coupled through a second coupling network to the first and second lines.

11. The circuit of claim 1 , wherein the state toggles in response to a change in the first output current and/or the second output current.

12. A method, comprising:
receiving a modulated differential signal from first and second lines;
generating a first output current in response to a voltage of the first line and a voltage of the second line, the first output current having a first direction, the voltage of the first line having a first polarity, and the voltage of the second line having a second polarity opposite the first polarity;
generating a second output current in response to the voltage of the first line and the voltage of the second line, the second output current having a second direction opposite the first direction; and
latching a state in response to the first and second output currents.

13. A circuit, comprising:
first and second lines to receive a modulated differential signal;
a first square-law detector, coupled to the first and second lines, to source a first output current in response to a voltage of the first line and a voltage of the second line, the first output current having a first direction, the voltage of the first line having a first polarity, the voltage of the second line having a second polarity opposite the first polarity, and the first square-law detector including: a first PMOS transistor having a gate coupled to the voltage of the first line; and a second PMOS transistor having a gate coupled to the voltage of the second line; wherein a drain of the first PMOS transistor is coupled to a drain of the second PMOS transistor;
a second square-law detector, coupled to the first and second lines, to sink a second output current in response to the voltage of the first line and the voltage of the second line, the second output current having a second direction opposite the first direction, and the second square-law detector including: a first NMOS transistor having a gate coupled to the voltage of the first line; and a second NMOS transistor having a gate coupled to the voltage of the second line; wherein a drain of the first NMOS transistor is coupled to a drain of the second NMOS transistor;
an NMOS load transistor coupled to sink the first output current from the drains of the first and second PMOS transistors;
a PMOS load transistor coupled to source the second output current to the drains of the first and second NMOS transistors; and
a cross-coupled latch including first and second inverters to latch a state in response to the first and second output currents, an output of the first inverter being coupled to an input of the second inverter, an output of the second inverter being coupled to an input of the first inverter, the input of the first inverter being coupled to the drains of the first and second PMOS transistors, and the input of the second inverter being coupled to the drains of the first and second NMOS transistors.

14. The circuit of claim 13 , wherein the first and second PMOS transistors and the first and second NMOS transistors are biased in accordance with an active or subthreshold mode of transconductance.

15. The circuit of claim 13 , wherein the state toggles in response to a change in the first output current and/or the second output current.

16. The circuit of claim 13 , further comprising a differential voltage output having first and second outputs to indicate an envelope of information encoded in the modulated differential signal, the first output being coupled to the drains of the first and second PMOS transistors, and the second output being coupled to the drains of the first and second NMOS transistors.

17. The circuit of claim 13 , further comprising a device to galvanically isolate a transmitter from the first and second square-law detectors, wherein the first and second lines are coupled through the device to receive the modulated differential signal from the transmitter.

18. The circuit of claim 17 , wherein: the device is a transformer; a secondary

Assignees

• Texas Instruments Inc

Inventors

• Sankaran Swaminathan
• Kramer Bradley Allen
• Haroun Baher S

Classifications

• H04B1/18

  Input circuits, e.g. for coupling to an antenna or a transmission line (coupling networks between antennas or lines and receivers independent of the nature of the receiver H03H) · CPC title

• H04B1/24 Primary

  the receiver comprising at least one semiconductor device having three or more electrodes · CPC title

• H04L25/0268

  with modulation and subsequent demodulation · CPC title

• H04L25/026

  Arrangements for coupling transmitters, receivers or transceivers to transmission lines; Line drivers (duplexing arrangements H04L5/14) · CPC title

• H04L25/0266

  Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling · CPC title