Isolation circuits for digital communications and methods to provide isolation for digital communications

Patent metadata

Field	Value
Publication number	US-9379746-B2
Application number	US-201514732313-A
Country	US
Kind code	B2
Filing date	Jun 5, 2015
Priority date	Jun 30, 2014
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

Isolation circuits for digital communications and methods to provide isolation for digital communications are disclosed. An example isolation circuit includes an isolation barrier, a burst encoder in a first circuit, and an edge pattern detector in a second circuit. The example isolation barrier electrically isolates the first circuit from the second circuit. The example burst encoder generates a first pattern in response to receiving a rising edge on an input signal and generates a second pattern in response to receiving a falling edge on the input signal. The example edge pattern detector detects the first pattern or the second pattern received from the burst encoder via the isolation barrier, sets an output signal at a first signal level in response to detecting the first pattern, and sets the output signal at a second signal level in response to detecting the second pattern.

First claim

What is claimed is:

1. An isolation circuit, comprising:
an isolation barrier to electrically isolate a first circuit from a second circuit;
a burst encoder in the first circuit, the burst encoder to:
generate a first pattern in response to receiving a rising edge on an input signal; and
generate a second pattern in response to receiving a falling edge on the input signal; and

an edge pattern detector in the second circuit, the edge pattern detector to:
detect the first pattern or the second pattern received from the burst encoder via the isolation barrier;
set an output signal at a first signal level in response to detecting the first pattern; and
set the output signal at a second signal level in response to detecting the second pattern;

wherein the burst encoder generates the first pattern by generating a first number of electrical pulses by outputting a first oscillating signal for a first time period;
wherein the burst encoder generates the second pattern by generating a second number of electrical pulses by outputting a second oscillating signal for the first time period, the second oscillating signal having a different frequency than the first oscillating signal; and
a divider to generate the first oscillating signal by dividing a third oscillating signal by a first divisor and to generate the second oscillating signal by dividing the third oscillating signal by a second divisor.

2. An isolation circuit, comprising:
an isolation barrier to electrically isolate a first circuit from a second circuit;
a burst encoder in the first circuit, the burst encoder to:
generate a first pattern in response to receiving a rising edge on an input signal; and
generate a second pattern in response to receiving a falling edge on the input signal; and

an edge pattern detector in the second circuit, the edge pattern detector to:
detect the first pattern or the second pattern received from the burst encoder via the isolation barrier;
set an output signal at a first signal level in response to detecting the first pattern; and
set the output signal at a second signal level in response to detecting the second pattern;

wherein the burst encoder generates the first pattern by generating a first number of electrical pulses by outputting a first oscillating signal for a first time period;
wherein the burst encoder generates the second pattern by generating a second number of electrical pulses by outputting a second oscillating signal for the first time period, the second oscillating signal having a different frequency than the first oscillating signal; and
wherein the burst encoder includes:
a rising edge detector to detect the rising edge and to generate a rising edge trigger signal in response to the detection of the rising edge;
a falling edge detector to detect the falling edge and to generate a falling edge trigger signal in response to the detection of the falling edge; and
a pulse modulator to modulate a carrier signal to generate the first number of electrical pulses in response to the rising edge trigger signal and to generate the second number of electrical pulses in response to the falling edge trigger signal.

3. An isolation circuit, comprising:
an isolation barrier to electrically isolate a first circuit from a second circuit;
a burst encoder in the first circuit, the burst encoder to:
generate a first pattern in response to receiving a rising edge on an input signal; and
generate a second pattern in response to receiving a falling edge on the input signal; and

an edge pattern detector in the second circuit, the edge pattern detector to:
detect the first pattern or the second pattern received from the burst encoder via the isolation barrier;
set an output signal at a first signal level in response to detecting the first pattern; and
set the output signal at a second signal level in response to detecting the second pattern;

wherein the burst encoder generates the first pattern by generating a first number of electrical pulses by outputting a first oscillating signal for a first time period;
wherein the burst encoder generates the second pattern by generating a second number of electrical pulses by outputting a second oscillating signal for the first time period, the second oscillating signal having a different frequency than the first oscillating signal; and
wherein the edge pattern detector includes:
a pulse counter to determine a number of sequential electrical pulses on an envelope signal between a first idle signal level on the input signal and a second idle signal level on the input signal; and
a count converter to set the output signal at the first signal level or the second signal level based on the number of the sequential electrical pulses determined by the pulse counter.

4. The isolation circuit in claim 3 , in which the pulse counter is to implement a state machine to determine the number of the sequential electrical pulses on the input signal during a time period occurring between the first idle signal level on the input signal and the second idle signal level on the input signal.

5. The isolation circuit as defined in claim 3 , in which the pulse counter is to start a timer in response to detecting a first electrical pulse on the input signal, and is to determine the number of the sequential electrical pulses occurring between the starting of the timer and a completion of the timer.

6. An isolation circuit, comprising:
an isolation barrier to electrically isolate a first circuit from a second circuit;
a burst encoder in the first circuit, the burst encoder to:
generate a first pattern in response to receiving a rising edge on an input signal; and
generate a second pattern in response to receiving a falling edge on the input signal; and

an edge pattern detector in the second circuit, the edge pattern detector to:
detect the first pattern or the second pattern received from the burst encoder via the isolation barrier;
set an output signal at a first signal level in response to detecting the first pattern; and
set the output signal at a second signal level in response to detecting the second pattern;

a first data speed identifier to:
determine a first data speed of the input signal;
when the first data speed satisfies a threshold data speed, cause the input signal to bypass the burst encoder; and
when the first data speed does not satisfy the threshold, cause the input signal to be input to the burst encoder; and

a second data speed identifier to:
detect a second data speed of a modulated signal output by the isolation barrier;
when the second data speed satisfies the threshold data speed, cause the modulated signal to bypass the edge pattern detector to set the output signal based on the modulated signal; and

when the second data speed does not satisfy the threshold data speed, cause the modulated signal to be input to the edge pattern detector to enable the edge pattern detector to detect the first pattern or the second pattern in the modulated signal.

7. A method, comprising:
generating a first signal pattern in a first voltage domain in response to receiving a first rising edge on an input signal;
transmitting the first signal pattern to an electrical isolation barrier;
detecting the first signal pattern received in a second voltage domain via the electrical isolation barrier;
in response to detecting the first signal pattern, outputting a second rising edge on an output signal in the second voltage domain;
generating a second signal pattern in the first voltage domain in response to receiving a first falling edge on the input signal, the second signal pattern being different than the first signal pattern;
transmitting the second signal pattern to the electrical isolation barrier;

Assignees

• Texas Instruments Inc

Inventors

• Kramer Bradley Allen
• Morgan Mark W
• Sankaran Swaminathan

Classifications

• H04B2001/0408

  with power amplifiers · CPC title

• H04B1/0475 Primary

  with means for limiting noise, interference or distortion (H04B1/0483 takes precedence) · CPC title

• H04L25/0266 Primary

  Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling · CPC title

• H04L25/069

  by detecting edges or zero crossings · CPC title

• H03F3/24

  of transmitter output stages · CPC title