Method of forming a light emitting diode structure and a light diode structure

US10186635B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10186635-B2
Application numberUS-201514918342-A
CountryUS
Kind codeB2
Filing dateOct 20, 2015
Priority dateMay 18, 2010
Publication dateJan 22, 2019
Grant dateJan 22, 2019

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Abstract

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A method of forming a vertical III-nitride based light emitting diode structure 5 and a vertical III-nitride based light emitting diode structure can be provided. The method comprises forming a III-nitride based light emitting structure on a silicon-oninsulator (SOI) substrate; forming a metal-based electrode structure on the III-nitride based light emitting structure; and removing the SOI substrate by a layer transfer process such that the metal-based electrode structure functions as a metal-based 10 substrate of the light emitting structure.

First claim

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The invention claimed is: 1. A vertical III-nitride based light emitting diode structure, the structure comprising: a metal-based substrate; and a III-nitride based light emitting structure for light emission formed on the metal-based substrate, the III-nitride based light emitting structure comprising a light-generating layer comprising a plurality of III-nitride heterostructures, wherein a Group III metal content in the light-generating layer is inhomogeneously formed in response to creation of a patterned silicon-on-insulator (SOI) substrate comprising one or more silicon overlayers having a thickness ranging from about 10 nm to about 300 nm and a patterned buried oxide or silicon dioxide layer having a thickness ranging from about 60 to about 400 nm for modulating light emission of the vertical III-nitride based light emitting diode structure. 2. The structure as claimed in claim 1 , further comprising a metal seed layer formed between the III-nitride based light emitting structure and the metal-based substrate for facilitating layer transfer of the III-nitride based light emitting diode structure from the patterned silicon-on-insulator (SOI) substrate. 3. The structure as claimed in claim 2 , wherein the seed layer comprises nickel having a thickness ranging from about 100 nm to about 1000 nm. 4. The structure as claimed in claim 2 , wherein the seed layer is electroplated to the metal-based substrate. 5. The structure as claimed in claim 1 , further comprising a reflective mirror layer capable of functioning as a p-type contact electrode, the mirror layer formed between the metal-based substrate and the III-nitride based light emitting structure. 6. The structure as claimed in claim 5 , wherein the reflective mirror layer comprises a plurality of layers selected from a group of material consisting of nickel, gold, platinum, silver, palladium and ruthenium. 7. The structure as claimed in claim 1 , further comprising photonic crystal (PhC) structures formed on an n-doped III-nitride layer of the III-nitride based light emitting diode structure, the PhC structures having lateral and vertical dimensions of less than about 400 nm. 8. The structure as claimed in claim 1 , further comprising photonic crystal (PhC) structures formed on an n-doped III-nitride layer of the III-nitride based light emitting diode structure, the PhC structures comprising periodic patterns of structures selected from a group consisting of nanopillars, nanoholes and nanopyramid structures. 9. The structure as claimed in claim 1 , further comprising an n-type contact electrode structure formed on the III-nitride based light emitting structure. 10. The structure as claimed in claim 9 , wherein the n-type contact electrode structure comprises a plurality of layers selected from a group of material consisting of titanium, aluminium, gold, chromium and nickel. 11. The structure as claimed in claim 1 , wherein the plurality of heterostructures of the light-generating layer comprise a plurality of InGaN/GaN quantum wells, and wherein an indium content in the plurality of InGaN/GaN quantum wells is inhomogeneous across the light-generating layer for modulating light emission of the vertical III-nitride based light emitting diode structure. 12. A vertical III-nitride based light emitting diode structure, the structure comprising, a patterned buried oxide layer of a silicon-on-insulator (SOI) substrate; a III-nitride based light emitting structure for light emission formed on the patterned SOI substrate, the III-nitride based light emitting structure comprising an active layer comprising a plurality of III-nitride heterostructures, wherein a Group III metal content in the active layer of the III-nitride based light emitting structure is inhomogeneously formed in response to creation of the patterned SOI substrate comprising one or more silicon overlayers having a thickness ranging from about 10 nm to about 300 nm and the patterned buried oxide layer having a thickness ranging from about 60 to about 400 nm for modulating an emission of the light emitting diode structure. 13. The structure as claimed in claim 12 , wherein the III-nitride based light emitting structure comprises one or more nitride-based buffer layers formed directly on the patterned SOI substrate. 14. The structure as claimed in claim 12 , wherein the plurality of heterostructures of the active layer comprise a plurality of InGaN/GaN quantum wells, and wherein an indium content in the plurality of InGaN/GaN quantum wells is inhomogeneous across the active layer for modulating light emission of the vertical III-nitride based light emitting diode structure.

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What does patent US10186635B2 cover?
A method of forming a vertical III-nitride based light emitting diode structure 5 and a vertical III-nitride based light emitting diode structure can be provided. The method comprises forming a III-nitride based light emitting structure on a silicon-oninsulator (SOI) substrate; forming a metal-based electrode structure on the III-nitride based light emitting structure; and removing the SOI subs…
Who is the assignee on this patent?
Agency Science Tech & Res, Agency Science Tech & Res
What technology area does this patent fall under?
Primary CPC classification H01L33/32. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 22 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).