Semiconductor device

Patent metadata

Field	Value
Publication number	US-10186606-B2
Application number	US-201615537644-A
Country	US
Kind code	B2
Filing date	Jan 13, 2016
Priority date	Jan 16, 2015
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

A semiconductor device includes: a semiconductor substrate having a drift layer; a base layer on the drift layer; a collector layer and a cathode layer arranged on the drift layer opposite to the base layer; multiple trenches penetrating the base layer and reaching the drift layer, and arranged along one direction; a gate electrode arranged in each trench via a gate insulating film; and an emitter region arranged in a surface portion of the base layer, and contacting with each trench. The semiconductor substrate includes an IGBT region having the emitter region and an FWD region in which an injection limiting region and a contact region are arranged in the surface portion of the base layer alternately along the one direction.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor substrate having a drift layer of a first conduction type;
a base layer of a second conduction type arranged on the drift layer;
a collector layer of the second conduction type and a cathode layer of the first conduction type arranged on the drift layer opposite to the base layer;
a plurality of trenches penetrating the base layer and reaching the drift layer, and extending along one direction of plane directions of the semiconductor substrate;
a gate insulating film arranged on a sidewall of each trench;
a gate electrode arranged on the gate insulating film; and
an emitter region of the first conduction type arranged in a surface portion of the base layer, and contacting with each trench, wherein:
a region of the semiconductor substrate functioning as an IGBT element is defined as an IGBT region;
a region of the semiconductor substrate functioning as an FWD element is defined as an FWD region;
the emitter region is arranged in the IGBT region;
in the surface portion of the base layer in the FWD region, an injection limiting region of the first conduction type having an impurity concentration higher than the drift layer and a contact region of the second conduction type having an impurity concentration higher than the base layer are arranged alternately along the one direction;
in the surface portion of the base layer in the IGBT region, another contact region of the second conduction type is arranged together with the emitter region;
the another contact region and the emitter region are arranged alternately along the one direction;
a ratio between a length of the emitter region in the IGBT region along the one direction and a length of the another contact region in the IGBT region along the one direction is defined as a first ratio;
a ratio between a length of the injection limiting region in the FWD region along the one direction and a length of the contact region in the FWD region along the one direction is defined as a second ratio; and
the first ratio is different from the second ratio.

2. The semiconductor device according to claim 1 , wherein:
a body region is arranged in the base layer under the emitter region, the contact region, and the injection limiting region; and
the body region has an impurity concentration higher than the base layer, extends along the one direction, contacts with the contact region, and is spaced apart from each trench.

3. A semiconductor device comprising:
a semiconductor substrate having a drift layer of a first conduction type;
a base layer of a second conduction type arranged on the drift layer;
a collector layer of the second conduction type and a cathode layer of the first conduction type arranged on the drift layer opposite to the base layer;
a plurality of trenches penetrating the base layer and reaching the drift layer, and extending along one direction of plane directions of the semiconductor substrate;
a gate insulating film arranged on a sidewall of each trench;
a gate electrode arranged on the gate insulating film; and
an emitter region of the first conduction type arranged in a surface portion of the base layer, and contacting with each trench, wherein:
a region of the semiconductor substrate functioning as an IGBT element is defined as an IGBT region;
a region of the semiconductor substrate functioning as an FWD element is defined as an FWD region;
the emitter region is arranged in the IGBT region;
in the surface portion of the base layer in the FWD region, an injection limiting region of the first conduction type having an impurity concentration higher than the drift layer and a contact region of the second conduction type having an impurity concentration higher than the base layer are arranged alternately along the one direction;
the semiconductor substrate further includes a cell region having the IGBT region and the FWD region, and an outer peripheral region surrounding the cell region and having the drift layer;
at least a part of the cell region located at a boundary between the cell region and the outer peripheral region is defined as the FWD region;
the base layer arranged in the cell region extends to the outer peripheral region on the drift layer; and
the collector layer is arranged on a portion of the drift layer in the outer peripheral region opposite to the base layer.

4. The semiconductor device according to claim 3 , wherein:
the injection limiting region is arranged only in the FWD region.

5. The semiconductor device according to claim 3 , wherein:
the collector layer is arranged on the drift layer opposite to the base layer in a boundary portion between the FWD region and the outer peripheral region.

6. The semiconductor device according claim 5 , wherein:
the semiconductor substrate has one surface located on a side of the base layer and an other surface located on a side of the collector layer or the cathode layer opposite to the one surface; and
the collector layer arranged in the FWD region is arranged from a boundary between the FWD region and the outer peripheral region, and is equal to or longer than a length between the one surface and the other surface of the semiconductor substrate.

7. A semiconductor device comprising:
a semiconductor substrate having a drift layer of a first conduction type;
a base layer of a second conduction type arranged on the drift layer;
a collector layer of the second conduction type and a cathode layer of the first conduction type arranged on the drift layer opposite to the base layer;
a plurality of trenches penetrating the base layer and reaching the drift layer, and extending along one direction of plane directions of the semiconductor substrate;
a gate insulating film arranged on a sidewall of each trench;
a gate electrode arranged on the gate insulating film; and
an emitter region of the first conduction type arranged in a surface portion of the base layer, and contacting with each trench, wherein:
a region of the semiconductor substrate functioning as an IGBT element is defined as an IGBT region;
a region of the semiconductor substrate functioning as an FWD element is defined as an FWD region;
the emitter region is arranged in the IGBT region;
in the surface portion of the base layer in the FWD region, an injection limiting region of the first conduction type having an impurity concentration higher than the drift layer and a contact region of the second conduction type having an impurity concentration higher than the base layer are arranged alternately along the one direction; and
an interval along the one direction between adjacent injection limiting regions of a plurality of injection limiting regions arranged in a boundary portion between the FWD region and the outer peripheral region is shorter than adjacent injection limiting regions of a plurality of injection limiting regions arranged in an inner rim portion of the boundary portion.

8. A semiconductor device comprising:
a semiconductor substrate having a drift layer of a first conduction type;
a base layer of a second conduction type arranged on the drift layer;
a collector layer of the second conduction type and a cathode layer of the first conduction type arranged on the drift layer opposite to the base layer;
a plurality of trenches penetrating the base layer and reaching the drift layer, and extending along one direction of plane directions of the semiconductor substrate;
a gate insulating film arranged on a sidewall of each trench;
a gate electrode arranged on the gate insulating film; and
an emitter region of the first conduction type arranged in a surface portion of the base layer, and contacting with each trench, wherein:
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Assignees

• Denso Corp

Inventors

• Sumitomo Masakiyo

Classifications

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H10D84/161

  IGBT having built-in components · CPC title

• H01L27/0761

  Electricity · mapped topic

• H01L27/0727

  Electricity · mapped topic