Semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-10186513-B2
Application number	US-201815884415-A
Country	US
Kind code	B2
Filing date	Jan 31, 2018
Priority date	Feb 3, 2017
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

A semiconductor device and method of forming the same, the semiconductor device includes bit lines, a transistor, a dielectric layer, plugs and a capping layer. The bit lines are disposed on a substrate within a cell region thereof, and the transistor is disposed on the substrate within a periphery region. The plugs are disposed in the dielectric layer, within the cell region and the periphery region respectively. The capping layer is disposed on the dielectric layer, and the capping layer disposed within the periphery region is between those plugs. That is, a portion of the dielectric layer is therefore between the capping layer and the transistor.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a substrate comprising a cell region and a periphery region;
a plurality of bit lines parallel disposed on the substrate within the cell region, wherein a composite spacer is disposed at two sides of each bit line and each composite spacer comprises a first layer, an air-gap layer and a third layer;
at least one transistor, disposed on the substrate within the periphery region;
a dielectric layer, disposed on the substrate and covered on the bit lines and the transistor;
a plurality of first plugs, disposed in the dielectric layer within the cell region;
a plurality of second plugs, disposed in the dielectric layer within the periphery region; and
a capping layer, disposed on the dielectric layer, the capping disposed within the periphery region being between the second plugs and a portion of the dielectric layer being between the capping layer and the transistor.

2. The semiconductor device according to claim 1 , wherein the capping layer and the dielectric layer comprise different materials.

3. The semiconductor device according to claim 1 , wherein the first layer and the third layer comprises a same material.

4. The semiconductor device according to claim 1 , wherein the capping layer comprise a same material as that of the first layer or the third layer.

5. The semiconductor device according to claim 1 , further comprising:
a spacer layer covered on the transistor, the spacer layer and the third layer comprising a same material.

6. The semiconductor device according to claim 1 , wherein top surfaces of the second plugs are level with a top surface of the capping layer.

7. The semiconductor device according to claim 6 , wherein the capping layer directly contacts the second plugs.

8. The semiconductor device according to claim 1 , wherein top surfaces of the first plugs are higher than top surfaces of the bit lines.

Assignees

• United Microelectronics Corp
• Fujian Jinhua Integrated Circuit Co Ltd

Inventors

• Chang Feng-Yi
• Lee Fu-Che
• Chen Chieh-Te

Classifications

• H10W20/072

  of dielectric parts comprising air gaps · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/46

  comprising air gaps · CPC title

• H10W20/081

  by forming openings in the dielectric parts · CPC title

• H10W20/056

  by filling conductive material into holes, grooves or trenches · CPC title