Semiconductor device, package, and vehicle

Patent metadata

Field	Value
Publication number	US-10186479-B2
Application number	US-201715426142-A
Country	US
Kind code	B2
Filing date	Feb 7, 2017
Priority date	Aug 29, 2014
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

A semiconductor device includes a metal plate capacitor that includes a heat-resistant metal plate and a capacitor unit including a sintered dielectric formed on at least one surface of the heat-resistant metal plate, a semiconductor chip disposed on the metal plate capacitor, a connector configured to electrically connect the semiconductor chip and the metal plate capacitor, and a protector configured to protect the semiconductor chip, the metal plate capacitor, and the connector.

First claim

What is claimed is:

1. A semiconductor device comprising:
a metal plate capacitor including a heat-resistant metal plate and a capacitor unit including a sintered dielectric formed on at least one surface of the heat-resistant metal plate, the heat-resistant metal plate containing aluminum in an amount of 0.5 mass % to 20 mass %, inclusive;
a semiconductor chip disposed on the metal plate capacitor;
a connector configured to electrically connect the semiconductor chip and the metal plate capacitor; and
a protector configured to protect the semiconductor chip, the metal plate capacitor, and the connector.

2. A semiconductor device comprising:
a metal plate capacitor including a heat-resistant metal plate, and a lower electrode, a sintered dielectric, and an upper electrode that are formed on at least one surface of the heat-resistant metal plate, the heat-resistant metal plate containing aluminum in an amount of 0.5 mass % to 20 mass %, inclusive;
a semiconductor chip disposed on the metal plate capacitor;
a resin substrate unit on which the heat-resistant metal plate and the semiconductor chip are disposed;
an upper chip connector configured to electrically connect the semiconductor chip and the upper electrode;
a lower chip connector configured to electrically connect the semiconductor chip and the lower electrode; and
a protector configured to protect the semiconductor chip, the metal plate capacitor, the upper chip connector, the lower chip connector, and a surface of the resin substrate unit.

3. The semiconductor device according to claim 2 , wherein the lower electrode and the heat-resistant metal plate are electrically connected with each other.

4. The semiconductor device according to claim 2 , wherein the lower electrode and the heat-resistant metal plate are connected with each other through a fabricated connection part formed in at least the metal plate capacitor.

5. The semiconductor device according to claim 2 , wherein
the heat-resistant metal plate further includes a back electrode, and
the back electrode is formed on a side of the heat-resistant metal plate, on which the lower electrode is not formed.

6. The semiconductor device according to claim 2 , wherein
the upper electrode includes an upper auxiliary electrode formed on a surface of the upper electrode, and
part of the upper chip connector is connected with the upper auxiliary electrode.

7. The semiconductor device according to claim 2 , wherein
the lower electrode includes a lower auxiliary electrode formed on a surface of the lower electrode, and
part of the lower chip connector is connected with the lower auxiliary electrode.

8. The semiconductor device according to of claim 2 , wherein a plurality of the upper electrodes insulated from each other in a pattern shape are formed on one surface of the sintered dielectric.

9. The semiconductor device according to of claim 2 , wherein a plurality of the semiconductor chips are disposed on one surface of the metal plate capacitor.

10. The semiconductor device according to of claim 2 , wherein
an insulating oxide layer is formed on a surface of the heat-resistant metal plate, and
at least the heat-resistant metal plate and the lower electrode are connected with each other through a fabricated connection part formed at an end part of the heat-resistant metal plate.

11. The semiconductor device according to of claim 2 , wherein
the upper electrode and the lower electrode are each a sintered electrode containing silver of 50 mass % to 100 mass % inclusive, and
the sintered dielectric is a sintered dielectric having a thickness of 3 μm to 50 μm inclusive and obtained through sintering.

12. The semiconductor device according to claim 2 , wherein
the heat-resistant metal plate includes a through-hole into which the semiconductor chip is inserted,
the upper electrode, the sintered dielectric, and the lower electrode are formed around the through-hole, and
the semiconductor chip is disposed in the through-hole.

13. The semiconductor device according to claim 2 , wherein
the metal plate capacitor includes an opening in which the sintered dielectric and the upper electrode are not formed,
the upper electrode and the sintered dielectric are formed around the opening, and
the semiconductor chip is disposed in the opening.

14. A semiconductor device comprising:
a lead frame;
a metal plate capacitor including a heat-resistant metal plate, and a lower electrode, a sintered dielectric, and an upper electrode that are formed on at least one surface of the heat-resistant metal plate, the heat-resistant metal plate containing aluminum in an amount of 0.5 mass % to 20 mass %, inclusive;
a semiconductor chip disposed on the metal plate capacitor;
an upper chip connector configured to electrically connect the semiconductor chip and the upper electrode;
a lower chip connector configured to electrically connect the semiconductor chip and the lower electrode;
a protector configured to protect the semiconductor chip, the metal plate capacitor, the upper chip connector, the lower chip connector, and at least part of the lead frame.

15. The semiconductor device according to claim 14 , wherein the lower electrode and the heat-resistant metal plate are electrically connected with each other.

16. The semiconductor device according to claim 14 , wherein the lower electrode and the heat-resistant metal plate are connected with each other through a fabricated connection part formed in at least the metal plate capacitor.

17. The semiconductor device according to claim 14 , wherein
the heat-resistant metal plate further includes a back electrode, and
the back electrode is formed on a side of the heat-resistant metal plate, on which the lower electrode is not formed.

18. The semiconductor device according to claim 14 , wherein
the upper electrode includes an upper auxiliary electrode formed on a surface of the upper electrode, and
part of the upper chip connector is connected with the upper auxiliary electrode.

19. The semiconductor device according to claim 14 , wherein
the lower electrode includes a lower auxiliary electrode formed on a surface of the lower electrode, and
part of the lower chip connector is connected with the lower auxiliary electrode.

20. The semiconductor device according to of claim 14 , wherein a plurality of the upper electrodes insulated from each other in a pattern shape are formed on one surface of the sintered dielectric.

21. The semiconductor device according to of claim 14 , wherein a plurality of the semiconductor chips are disposed on one surface of the metal plate capacitor.

22. The semiconductor device according to of claim 14 , wherein
an insulating oxide layer is formed on a surface of the heat-resistant metal plate, and
at least the heat -resistant metal plate and the lower electrode are connected with each other through a fabricated connection part formed at an end part of the heat-resistant metal plate.

23. The semiconductor device according to of claim 14 , wherein
the upper electrode and the lower electrode are each a sintered electrode containing silver of 50 mass % to 100 mass % inclusive, and
the sintered dielectric is a sintered dielectric having a thickness of 3 μm to 50 μm inclusive and obtained through sintering.

24. The semiconductor device according to claim 14 , wherein
the heat-resistant metal plate includes a through-hole into which

Assignees

• Panasonic Ip Man Co Ltd

Inventors

• Katsumura Hidenori
• Tokunaga Shinya
• Sumita Masaya
• Yoshida Hiroyoshi
• Sugaya Yasuhiro
• Uriu Kazuhide
• Shibata Osamu

Classifications

• H10W90/758

  between a chip and a stacked discrete passive device · CPC title

• H10W90/753

  between laterally-adjacent chips · CPC title

• H10W90/752

  between stacked chips · CPC title

• H10W90/732

  between stacked chips · CPC title

• H10W90/728

  between a chip and a stacked discrete passive device, e.g. resistors, capacitors or inductors · CPC title