Multiprocessor system with improved secondary interconnection network

Patent metadata

Field	Value
Publication number	US-10185672-B2
Application number	US-201715437343-A
Country	US
Kind code	B2
Filing date	Feb 20, 2017
Priority date	Dec 13, 2012
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

Embodiments of a multiprocessor system are disclosed that may include a plurality of processors interspersed with a plurality of data memory routers, a plurality of bus interface units, a bus control circuit, and a processor interface circuit. The data memory routers may be coupled together to form a primary interconnection network. The bus interface units and the bus control circuit may be coupled together in a daisy-chain fashion to form a secondary interconnection network. Each of the bus interface units may be configured to read or write data or instructions to a respective one of the plurality of data memory routers and a respective processor. The bus control circuit coupled with the processor interface circuit may be configured to function as a bidirectional bridge between the primary and secondary networks. The bus control circuit may also couple to other interface circuits and arbitrate their access to the secondary network.

First claim

What is claimed is:

1. A multichip system, comprising:
a first integrated circuit chip including:
a first plurality of processors;
a plurality of memories;
a first plurality of routers coupled together to form a first primary interconnection network;
a plurality of interface units coupled together to form a secondary interconnection network, wherein each interface unit is coupled to a respective processor of the first plurality of processors and a respective router of the first plurality of routers;
a bus controller coupled to at least a particular interface unit of the plurality of interface units;
wherein the first plurality of processors, the plurality of memories, and the first plurality of routers are coupled together in an interspersed fashion; and

a second integrated circuit chip coupled to the first integrated circuit chip via an inter-chip interconnect, wherein the second integrated circuit chip includes a second plurality of processors;
wherein a particular processor of the second plurality of processors is configured to send first data, via the inter-chip interconnect, to the bus controller; and
wherein the bus controller is configured to:
relay the first data to the particular interface unit; and
arbitrate requests for access to the particular interface unit from a plurality of circuit blocks.

2. The multichip system of claim 1 , wherein the bus controller is further configured to receive second data from the particular interface unit, and relay the second data to the particular processor of the second plurality of processors via the inter-chip interconnect.

3. The multichip system of claim 1 , wherein to send the first data, the particular processor of the second plurality of processors is further configured to send the first data to a specified router of the first plurality of routers, wherein the specified router is coupled to the bus controller via a processor interface unit.

4. The multichip system of claim 1 , wherein the second integrated circuit chip further includes a second plurality of routers coupled together to form a second primary interconnection network.

5. The multichip system of claim 4 , wherein the first primary interconnection network is coupled to the second primary interconnection network to form the inter-chip interconnect.

6. The multichip system of claim 5 , wherein the first integrated circuit chip further includes a processor interface block coupled to the bus controller and also coupled to a particular router of the first plurality of routers, wherein the processor interface block is configured receive the first data from a given processor of the second plurality of processors via the first plurality of routers, the inter-chip interconnect, and the second plurality of routers.

7. The multichip system of claim 1 , wherein the plurality of circuit blocks includes a processor interface circuit, and a boot controller circuit.

8. A method for communicating in a multichip system, the method comprising:
establishing a communication path from a particular processor of a first plurality of processors included in a first integrated circuit chip to a bus controller included in a second integrated circuit chip, wherein the bus controller is coupled to a particular interface unit of a plurality of interface units, included in the second integrated circuit chip, coupled together to form a secondary interconnection network;
sending first data via the communication path from the particular processor to the bus controller; and
relaying the first data, by the bus controller, to the particular interface unit.

9. The method of claim 8 , wherein the first integrated circuit chip includes a first plurality of routers coupled to form a first primary interconnection network, and the second integrated circuit chip includes a second plurality of routers coupled to form a second primary interconnection network.

10. The method of claim 9 , wherein establishing the communication path includes coupling the first primary interconnection network to the second primary interconnection network.

11. The method of claim 9 , wherein sending the first data includes sending the first data to a specified router of the second plurality of routers, wherein the specified router is coupled to the bus controller via a processor interface unit.

12. The method of claim 8 , further comprising receiving, by the bus controller, second data from the particular interface unit, and relaying the second data to the particular processor of the first plurality of processors via an inter-chip interconnect.

13. The method of claim 8 , further comprising receiving, by the bus controller, messages from two or more processors of a second plurality of processors.

14. A system, comprising:
a first integrated circuit chip including:
a first plurality of processors;
a plurality of memories;
a first plurality of data memory routers coupled together to form a first primary interconnection network, wherein each data memory router includes a plurality of communication ports, a memory, and a routing engine;
a plurality of interface units coupled together to form a secondary interconnection network, wherein each interface unit is coupled to a respective processor of the first plurality of processors and a respective router of the first plurality of data memory routers;
a bus controller coupled to at least a particular interface unit of the plurality of interface units;
wherein the first plurality of processors, the plurality of memories, and the first plurality of data memory routers are coupled together in an interspersed fashion; and

a second integrated circuit chip coupled to the first integrated circuit chip via an inter-chip interconnect, wherein the second integrated circuit chip includes a second plurality of processors;
wherein a particular processor of the second plurality of processors is configured to send first data, via the inter-chip interconnect, to the bus controller; and
wherein the bus controller is configured to:
relay the first data to the particular interface unit; and
arbitrate requests for access to the particular interface unit from a plurality of circuit blocks.

15. The system of claim 14 , wherein the bus controller is further configured to receive second data from the particular interface unit, and relay the second data to the particular processor of the second plurality of processors via the inter-chip interconnect.

16. The system of claim 14 , wherein to send the first data, the particular processor of the second plurality of processors is further configured to send the first data to a specified data memory router of the first plurality of data memory routers, wherein the specified data memory router is coupled to the bus controller via a processor interface unit.

17. The system of claim 14 , wherein the second integrated circuit chip further includes a second plurality of data memory routers coupled together to form a second primary interconnection network.

18. The system of claim 17 , wherein the first primary interconnection network is coupled to the second primary interconnection network to form the inter-chip interconnect.

19. The system of claim 18 , wherein the first integrated circuit chip further includes a processor interface block coupled to the bus controller and also coupled to a particular data memory router of the first plurality of data memory routers, wherein the processor interface block is configured receive the first data from a given processor of the second plurality of processors via the

Assignees

• Coherent Logix Inc

Inventors

• Dobbs Carl S
• Trocino Michael R

Classifications

• G06F13/4068

  Electrical coupling · CPC title

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F13/4027

  using bus bridges (G06F13/4022 takes precedence) · CPC title

• G06F13/1652 Primary

  in a multiprocessor architecture (interprocessor communication using common memory G06F15/167) · CPC title