Method and apparatus to reduce idle link power in a platform

Patent metadata

Field	Value
Publication number	US-10185385-B2
Application number	US-201615180466-A
Country	US
Kind code	B2
Filing date	Jun 13, 2016
Priority date	Jul 1, 2011
Publication date	Jan 22, 2019
Grant date	Jan 22, 2019

Abstract

A method and apparatus to reduce the idle link power in a platform. In one embodiment of the invention, the host and its coupled endpoint(s) in the platform each has a low power idle link state that allows disabling of the high speed link circuitry in both the host and its coupled endpoint(s). This allows the platform to reduce its idle power as both the host and its coupled endpoint(s) are able to turn off their high speed link circuitry in one embodiment of the invention.

First claim

What is claimed is:

1. An apparatus comprising:
a first device comprising:
a port, wherein the port is to enable a connection between the first device and a second device, and the port to:
monitor a logical state of a bidirectional open-drain sideband signal to determine whether the sideband signal is de-asserted;
determine whether a latency tolerance reporting (LTR) value is greater than or equal to a threshold value corresponding to a particular one of a set of sub-states of a low-power link state; and
determine a request to transition from a first one of the set of sub-states to another one of at least two other sub-states in the plurality of sub-states based on a de-assertion of the sideband signal and whether the LTR value is greater than or equal to the threshold value, a reference clock is to be used in the first sub-state and is not used in each of the at least two other sub-states, the at least two other sub-states comprises the particular sub-state, and the particular sub-state is to be entered from the first sub-state when the sideband signal is de-asserted and the LTR value is greater than or equal to the threshold value.

2. The apparatus of claim 1 , wherein the port is compliant with a Peripheral Component Interconnect Express (PCIe)-based protocol.

3. The apparatus of claim 1 , wherein the set of sub-states comprises sub-states of a particular low-power link state.

4. The apparatus of claim 3 , wherein the port is to enter an active link state and transition from the active link state to the particular low-power link state.

5. The apparatus of claim 4 , wherein the port is to transition from the particular low-power link state to the first sub-state.

6. A system comprising:
a first device;
a second device to connect to the first device over a link, wherein the second device comprises link circuitry to:
monitor a logical state of a bidirectional open-drain sideband signal to determine whether the sideband signal is de-asserted;
determine whether a latency tolerance reporting (LTR) value is greater than or equal to a threshold value corresponding to a particular one of a set of sub-states of a low-power link state; and
determine a request to transition from a first one of the plurality of sub-states to another one of at least two other sub-states in the plurality of sub-states based on a de-assertion of the sideband signal and whether the LTR value is greater than or equal to the threshold value, a reference clock is to be used in the first sub-state and is not used in each of the at least two other sub-states, the at least two other sub-states comprises the particular sub-state, and the particular sub-state is to be entered from the first sub-state when the sideband signal is de-asserted and the LTR value is greater than or equal to the threshold value.

7. The system of claim 6 , wherein the system comprises a server computer.

8. The system of claim 6 , wherein the system comprises a personal computing device.

9. The system of claim 6 , wherein the system comprises a mobile computing device.

10. The system of claim 6 , wherein the port is compliant with a Peripheral Component Interconnect Express (PCIe)-based protocol.

11. A system comprising:
means for monitoring a logical state of a bidirectional open-drain sideband signal to determine whether the sideband signal is de-asserted;
means for determining whether a latency tolerance reporting (LTR) value is greater than or equal to a threshold value corresponding to a particular one of a set of sub-states of a low-power link state; and
means for determining a request to transition from a first one of the set of sub-states to another one of at least two other sub-states in the plurality of sub-states based on a de-assertion of the sideband signal and whether the LTR value is greater than or equal to the threshold value, a reference clock is to be used in the first sub-state and is not used in each of the at least two other sub-states, the at least two other sub-states comprises the particular sub-state, and the particular sub-state is to be entered from the first sub-state when the sideband signal is de-asserted and the LTR value is greater than or equal to the threshold value.

Assignees

• Intel Corp

Inventors

• Diefenbaugh Paul S
• Gough Robert E
• Bachrach Yuval
• Hunsaker Mikal C
• Ben-Tal Rafi
• Pardo Ilan
• Prat Gideon
• Harriman David J

Classifications

• G06F1/3278

  Power saving in modem or I/O interface · CPC title

• Y02D10/157

  Cross-Sectional Technologies · mapped topic

• G06F1/325 Primary

  Power saving in peripheral device · CPC title

• Y02D10/171

  Cross-Sectional Technologies · mapped topic

• G06F1/3234

  Power saving characterised by the action undertaken · CPC title