FinFet having dual vertical spacer and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10181527-B2
Application number	US-201615169621-A
Country	US
Kind code	B2
Filing date	May 31, 2016
Priority date	Oct 16, 2015
Publication date	Jan 15, 2019
Grant date	Jan 15, 2019

Abstract

A field effect transistor (FET) structure includes: a gate; a first spacer having a first dielectric constant at a first region adjacent to the gate; and a second spacer having a second dielectric constant that is greater than the first dielectric constant at a second region adjacent to the gate.

First claim

What is claimed is:

1. A field effect transistor (FET) structure comprising:
a fin;
a gate on the fin, the gate comprising a gate dielectric;
a shallow trench insulator surrounding a portion of the fin;
at least one of a source electrode and a drain electrode on the fin;
a first spacer on the fin and the shallow trench insulator, the first spacer having a first dielectric constant at a first region adjacent to the gate; and
a second spacer on the fin and the first spacer, the second spacer having a second dielectric constant that is greater than the first dielectric constant at a second region adjacent to the gate,
wherein the first spacer extends from below a top surface of the fin to the top surface of the fin, wherein a portion of the first spacer is between the gate and at least one of the source electrode and the drain electrode, and the second spacer only extends from the top surface of the fin towards a top of the gate, wherein a portion of the second spacer is between the gate and the at least one of the source electrode and the drain electrode,
wherein a bottom surface of the at least one of the source electrode and the drain electrode is above a bottom surface of the gate dielectric and below the top surface of the fin, and
wherein a top surface of the at least one of the source electrode and the drain electrode is coplanar with a top surface of the gate dielectric.

2. The FET structure of claim 1 , wherein a spacer material for the second spacer has a sufficient etch resistance to a contact etch processing, and wherein the spacer material for the second spacer has a higher etch resistance to the contact etch processing than that of the first spacer.

3. The FET structure of claim 1 , wherein the first spacer and the second spacer have a same thickness, and wherein each of the first spacer and the second spacer comprises a single insulating material or multiple insulating materials.

4. The FET structure of claim 1 , wherein the first spacer has a dielectric constant less than 4, and the second spacer has a dielectric constant greater than 4 and less than 7.

5. The FET structure of claim 1 , wherein the FET structure is a finFET structure comprising the fin.

6. The finFET structure of claim 5 , wherein the first spacer reduces gate-to-source, gate-to-fin sidewall, and/or gate-to-drain fringe capacitance coupling.

7. The finFET structure of claim 5 , wherein the first spacer comprises at least one of carbon, hydrogen, or fluorine doped oxides of silicon, and the second spacer comprises at least one of SiON, SiOCN, SiCBN, SiCN, or Si3N4.

8. A fin field effect transistor (FinFET) device comprising:
a fin;
a gate, a source electrode, and a drain electrode on the fin, the gate comprising a gate dielectric;
a shallow trench insulator surrounding a portion of the fin;
a first spacer on the shallow trench insulator and the fin between the gate and the source electrode and/or between the gate and the drain electrode, the first spacer having a first dielectric constant; and
a second spacer on the first spacer and the fin between the gate and the source electrode and/or between the gate and the drain electrode, the second spacer having a second dielectric constant that is greater than the first dielectric constant,
wherein the first spacer extends from below a top surface of the fin to the top surface of the fin, wherein a portion of the first spacer is between the gate and the source electrode and/or the drain electrode, and the second spacer only extends from the top surface of the fin towards a top of the gate, wherein a portion of the second spacer is between the gate and the source electrode and/or the drain electrode,
wherein the second spacer is entirely separated from the shallow trench insulator between the gate and the source electrode and/or the drain electrode by the first spacer,
wherein a bottom surface of the source electrode and/or the drain electrode is above a bottom surface of the gate dielectric and below the top surface of the fin, and
wherein a top surface of the source electrode and/or the drain electrode is coplanar with a top surface of the gate dielectric.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Palle Dharmendar Reddy
• Obradovic Borna
• Hong Joon Goo
• Rodder Mark

Classifications

• H01L29/785 Primary

  Electricity · mapped topic

• H01L29/6656

  Electricity · mapped topic

• H01L29/6653

  Electricity · mapped topic

• H01L29/66795

  Electricity · mapped topic

• H10D30/6219

  characterised by the source or drain electrodes · CPC title