Transistor structure with improved unclamped inductive switching immunity

Patent metadata

Field	Value
Publication number	US-10181523-B2
Application number	US-201715659539-A
Country	US
Kind code	B2
Filing date	Jul 25, 2017
Priority date	Aug 21, 2014
Publication date	Jan 15, 2019
Grant date	Jan 15, 2019

Abstract

A laterally diffused metal oxide semiconductor (LDMOS) transistor structure with improved unclamped inductive switching immunity. The LDMOS includes a substrate and an adjacent epitaxial layer both of a first conductivity type. A gate structure is above the epitaxial layer. A drain region and a source region, both of a second conductivity type, are within the epitaxial layer. A channel is formed between the source and drain region and arranged below the gate structure. A body structure of the first conductivity type is at least partially formed under the gate structure and extends laterally under the source region, wherein the epitaxial layer is less doped than the body structure. A conductive trench-like feed-through element passes through the epitaxial layer and contacts the substrate and the source region. The LDMOS includes a tub region of the first conductivity type formed under the source region, and adjacent laterally to and in contact with said body structure and said trench-like feed-through element.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an epitaxial layer located over a doped substrate layer, said epitaxial layer comprising a source region and a drain region, said epitaxial layer further comprising a body structure;
a gate structure above said epitaxial layer;
an electrically conductive trench-like feed-through element comprising a barrier layer, wherein said trench-like feed-through element passes through said epitaxial layer and also contacts said substrate layer and said source region; and
a first tub region under said source region and extending laterally under said gate structure, and adjacent laterally to and in contact with said body structure, and wherein said first tub region is in contact with said trench-like feed-through element.

2. The semiconductor device of claim 1 , further comprising a second tub region located at least partially below said first tub region and extending laterally under said gate structure.

3. The semiconductor device of claim 2 , wherein said second tub region contacts said substrate layer.

4. The semiconductor device of claim 2 , wherein said body structure is less doped than said first tub region, and wherein said second tub region is less doped than said first tub region.

5. The semiconductor device of claim 1 , further comprising a first clamp region located under said drain region.

6. The semiconductor device of claim 5 , further comprising a second clamp region located under said drain region.

7. The semiconductor device of claim 6 , wherein said first clamp region is less doped than said second clamp region.

8. The semiconductor device of claim 6 , wherein said first clamp region and said second clamp region extend laterally from said drain region toward said gate structure, and wherein said second clamp region extends further laterally toward said gate structure than said first clamp region.

9. The semiconductor device of claim 1 , wherein said drain region comprises:
a first doped region accessible to a drain contact; and
a second doped region located at least partially under said first region in said epitaxial layer, wherein said second doped region is less doped than said first doped region and wherein said second doped region separates said first doped region and said first clamp region.

10. The semiconductor device of claim 9 , further comprising a first clamp region that is coarsely aligned with an edge of said first doped region.

11. The semiconductor device of claim 9 , further comprising a first clamp region that is coarsely aligned within an edge of said second doped region.

12. A semiconductor transistor structure, comprising:
a substrate of a first conductivity type;
an epitaxial layer adjacent to said substrate;
a gate structure located above said epitaxial layer,
a drain region of a second conductivity type within said epitaxial layer;
a source region of said second conductivity type within said epitaxial layer;
a body structure of said first conductivity type within said epitaxial layer at least partially formed under said gate structure and extending laterally under said source region;
an electrically conductive trench-like feed-through element comprising a barrier layer, wherein said trench-like feed-through element passes through said epitaxial layer and contacts said substrate and also passes through and contacts said source region; and
a first tub region of said first conductivity type located under said source region and under said gate structure, and adjacent laterally to and in contact with said body structure, and in contact with said trench-like feed-through element.

13. The semiconductor transistor structure of claim 12 , wherein said body structure is less doped than said first tub region.

14. The semiconductor transistor structure of claim 12 , further comprising a second tub region formed at least partially below said first tub region and extending laterally under said gate structure, wherein said second tub region is less doped than said first tub region.

15. The semiconductor transistor structure of claim 14 , wherein said second tub region contacts said substrate.

16. The semiconductor transistor structure of claim 12 , wherein said drain region comprises:
a first region accessible to a drain contact and spaced apart from said gate structure; and
a second region and located at least partially under said first region within said epitaxial layer, wherein said second region extends to at least partially under said gate structure, wherein said second region is less doped than said first region, wherein said second region is coarsely aligned with an edge of said gate structure.

17. The semiconductor transistor structure of claim 16 , further comprising a first clamp region of said first conductivity type located under said drain region and coarsely aligned with an edge of said first region of said drain region.

18. The semiconductor transistor structure of claim 17 , further comprising a second clamp region of said first conductivity type located under said drain region, wherein said first clamp region and said second clamp region extend laterally from said drain region toward said gate structure, and wherein said second clamp region extends further laterally toward said gate structure than said first clamp region.

19. The semiconductor transistor structure of claim 16 , further comprising a first clamp region of said first conductivity type located under said drain region and coarsely aligned with an edge of said second region of said drain region.

20. The semiconductor transistor structure of claim 19 , further comprising a second clamp region of said first conductivity type located under said drain region, wherein said first clamp region and said second clamp region extend laterally from said drain region toward said gate structure, and wherein said second clamp region extends further laterally toward said gate structure than said first clamp region.

Assignees

• Vishay Siliconix

Inventors

• Zhang Wenjie
• Bobde Madhur
• Chen Qufei
• Terrill Kyle

Classifications

• H10P30/222

  characterised by the angle between the ion beam and the crystal planes or the main crystal surface (characterised by the angle between the ion beam and the mask H10P30/221) · CPC title

• H01L29/4175

  Electricity · mapped topic

• H01L29/66712

  Electricity · mapped topic

• H01L29/402

  Electricity · mapped topic

• H01L29/0623

  Electricity · mapped topic