Semiconductor memory devices and methods for manufacturing the same

Patent metadata

Field	Value
Publication number	US-10181476-B2
Application number	US-201615087127-A
Country	US
Kind code	B2
Filing date	Mar 31, 2016
Priority date	Mar 31, 2015
Publication date	Jan 15, 2019
Grant date	Jan 15, 2019

Abstract

Semiconductor memory devices and methods for manufacturing the same are provided. The device may include vertical channel structures that are two-dimensionally arranged on a substrate and vertically extend from the substrate. The device may also include bit lines on the vertical channel structures, and each of the bit lines may be commonly connected to the vertical channel structures arranged in a first direction. The device may further include common source lines that extend between the vertical channel structures in a second direction intersecting the first direction and a source strapping line that is disposed at the same vertical level as the bit lines and electrically connects the common source lines to each other.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a plurality of vertical channel structures on a substrate, the plurality of vertical channel structures vertically extending from the substrate;
a plurality of bit lines on the plurality of vertical channel structures, each of the plurality of bit lines being commonly connected to ones of the plurality of vertical channel structures, wherein the plurality of bit lines are spaced apart from each other in a first direction;
a common source region extending in a second direction, wherein the second direction intersects the first direction, and both the first direction and the second direction are horizontal directions, and wherein ones of the plurality of bit lines overlap the common source region;
a plurality of common source lines extending in the second direction on the substrate, wherein one of the plurality of common source lines extends between a first one of the plurality of vertical channel structures and a second one of the plurality of vertical channel structures, and wherein the one of the plurality of common source lines overlaps and is electrically connected to the common source region; and
a source strapping line electrically connected to the plurality of common source lines, a lower surface of the source strapping line and lower surfaces of the plurality of bit lines being at an equal level.

2. The semiconductor memory device of claim 1 , wherein a width of the source strapping line in the second direction is greater than a width of each of the plurality of bit lines in the second direction.

3. The semiconductor memory device of claim 1 , further comprising:
a plurality of contacts, each of the plurality of contacts overlapping a respective one of the plurality of common source lines in plan view,
wherein ones of the plurality of contacts electrically connect respective ones of the plurality of vertical channel structures to respective ones of the plurality of bit lines, and
wherein the source strapping line overlaps at least two of the plurality of contacts and the one of the plurality of common source lines.

4. The semiconductor memory device of claim 3 , further comprising:
a plurality of conductive lines, wherein each of the plurality of conductive lines is connected to a bottom surface of one of the plurality of contacts, and
wherein each of the plurality of conductive lines intersects a respective one of the plurality of common source lines and extends on the plurality of vertical channel structures.

5. The semiconductor memory device of claim 4 , wherein ones of the plurality of conductive lines intersecting the respective one of the plurality of common source lines have asymmetrical lengths with respect to the respective one of the plurality of common source lines.

6. The semiconductor memory device of claim 4 , wherein the plurality of conductive lines extend in the first direction, and
wherein each of the plurality of conductive lines comprises an offset portion that overlaps a respective one of the plurality of common source lines in plan view and is offset from the first direction toward the second direction.

7. The semiconductor memory device of claim 4 , wherein the plurality of common source lines comprise a first common source line and a second common source line adjacent to the first common source line,
wherein the plurality of conductive lines extend in the first direction and comprise a first conductive line intersecting the first common source line and a second conductive line intersecting the second common source line,
wherein the first conductive line comprises a first offset portion that is offset from the first direction toward the second direction and overlaps the first common source line in plan view, and
wherein the second conductive line comprises a second offset portion that is offset from the first direction toward a third direction that is opposite to the second direction and overlaps the second common source line in plan view.

8. The semiconductor memory device of claim 3 , wherein the plurality of common source lines comprise a first common source line and a second common source line adjacent to the first common source line,
wherein the plurality of bit lines comprise odd-numbered bit lines and even-numbered bit lines arranged in the second direction in an alternating sequence,
wherein each of the odd-numbered bit lines is connected to a respective one of first ones of the plurality of contacts that overlap the first common source line in plan view, and
wherein each of the even-numbered bit lines is connected to a respective one of second ones of the plurality of contacts that overlap the second common source line in plan view.

9. The semiconductor memory device of claim 1 , wherein a lower surface of the one of the plurality of common source lines faces the substrate and is closer to the substrate than upper surfaces of the first one and second one of the plurality of vertical channel structures.

10. A semiconductor memory device comprising:
an electrode structure on a substrate, the electrode structure including a plurality of electrodes vertically stacked on the substrate;
a plurality of vertical channel structures extending through the electrode structure and being connected to the substrate;
first and second common source lines at respective opposing sides of the electrode structure, the first and second common source lines extending in a first direction;
a plurality of contacts on the first and second common source lines, the plurality of contacts being arranged in the first direction;
a plurality of bit lines extending in a second direction that intersects the first direction, each of the plurality of bit lines being electrically connected to one of the plurality of vertical channel structures; and
a source strapping line electrically connecting the first and second common source lines to each other,
wherein each of the first and second common source lines is connected to the source strapping line through at least two of the plurality of contacts interposed therebetween.

11. The semiconductor memory device of claim 10 , wherein a number of first ones of the plurality of contacts connecting the first common source line to the source strapping line is different from a number of second ones of the plurality of contacts connecting the second common source line to the source strapping line.

12. The semiconductor memory device of claim 10 , further comprising:
a plurality of conductive lines on the plurality of vertical channel structures and the first and second common source lines,
wherein each of the first and second common source lines is connected to the source strapping line through at least two of the plurality of conductive lines.

13. The semiconductor memory device of claim 10 , wherein the plurality of bit lines comprises odd-numbered bit lines and even-numbered bit lines arranged in the first direction in an alternating sequence,
wherein each of the odd-numbered bit lines is connected to a respective one of first ones of the plurality of contacts overlapping the first common source line in plan view, and
wherein each of the even-numbered bit lines is connected to a respective one of second ones of the plurality of contacts overlapping the second common source line in plan view.

14. The semiconductor memory device of claim 10 , wherein the source strapping line overlaps the at least two of the plurality of contacts and one of the first and second common source lines.

15. The semiconductor memory device of claim 10 , wherein a lower surface of the source strapping l

Assignees

• Kim Jongwon
• Rho Keejeong
• Won Jin Yeon
• Lim Tae Wan
• Park Woohyun
• Samsung Electronics Co Ltd

Inventors

• Kim Jongwon
• Rho Keejeong
• Won Jin-Yeon
• Lim Tae-Wan
• Park Woohyun

Classifications

• H01L27/11565

  Electricity · mapped topic

• H01L27/11582 Primary

  Electricity · mapped topic

• H10B43/10 Primary

  characterised by the top-view layout · CPC title

• H10B43/27 Primary

  the channels comprising vertical portions, e.g. U-shaped channels · CPC title