Memory system

Patent metadata

Field	Value
Publication number	US-10180796-B2
Application number	US-201615294119-A
Country	US
Kind code	B2
Filing date	Oct 14, 2016
Priority date	Oct 16, 2015
Publication date	Jan 15, 2019
Grant date	Jan 15, 2019

Abstract

A memory system includes: a plurality of first memory devices directly or indirectly coupled to one another, each first memory device including a first memory and a first memory controller suitable for controlling the first memory to store data; a second memory device including a second memory and a second memory controller suitable for controlling the second memory to store data; and a multi-processor including a plurality of processors, each processor executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices.

First claim

What is claimed is:

1. A memory system comprising:
a plurality of first memory devices directly or indirectly coupled to one another, each first memory device including a first memory and a first memory controller configured to control the first memory to store data;
a second memory device including a second memory and a second memory controller configured to control the second memory to store data; and
a multi-processor including a plurality of processors, each processor executing an operating system (OS) and an application to access a data storage memory through the first and second memory devices,
wherein the first and second memories are separated from the multi-processor,
wherein the second memory controller transfers a signal between a corresponding one among the plurality of processors and the second memory device based on a value of a handshaking information field included in the signal, and
wherein the value of the handshaking information field indicates the signal as one of a data request signal from the corresponding processor to the second memory, a data ready signal from the second memory to the corresponding processor and a session start signal from the corresponding processor to the second memory.

2. The memory system of claim 1 , further comprising a coherency manager commonly coupled to the plurality of first memory devices through a bus, and configured to manage a data coherency among the plurality of first memory devices.

3. The memory system of claim 2 ,
wherein the coherency manager permits the data coherency to at least one among the plurality of first memory devices in response to a coherency request provided from the at least one first memory device, and
wherein the coherency manager controls the plurality of first memory devices to exchange a coherency information with one another.

4. The memory system of claim 1 , wherein the second memory controller includes:
a handshaking interface configured to transfer the signal between the second memory device and the corresponding processor; and
a register configured to temporarily store data read out from the second memory.

5. The memory system of claim 1 , wherein the data request signal includes a command and an address for the second memory device.

6. The memory system of claim 1 ,
wherein the second memory controller includes a storage unit, and
wherein the second memory controller reads data from the second memory and temporarily stores the read data in the storage unit in response to the data request signal.

7. The memory system of claim 6 , wherein the second memory controller provides the data ready signal to the corresponding processor when the second memory controller temporarily stores the read data in the storage unit in response to the data request signal.

8. The memory system of claim 7 , wherein the corresponding processor provides the second memory controller with the session start signal to receive the read data temporarily stored in the storage unit in response to the data ready signal.

9. The memory system of claim 1 , wherein the second memory device is a nonvolatile memory device.

10. A memory system comprising:
a plurality of first memory devices directly or indirectly coupled to one another, each first memory device including a first memory and a first memory controller configured to control the first memory to store data;
a second memory device including a second memory and a second memory controller configured to control the second memory to store data; and
a multi-processor including a plurality of processors, each processor accessing the first and second memories,
wherein the second memory controller transfers a signal between a corresponding one among the plurality of processors and the second memory device based on a value of a handshaking information field included in the signal, and
wherein the value of the handshaking information field indicates the signal as one of a data request signal from the corresponding processor to the second memory, a data ready signal from the second memory to the corresponding processor and a session start signal from the corresponding processor to the second memory.

11. The memory system of claim 10 , further comprising a coherency manager commonly coupled to the plurality of first memory devices through a bus, and configured to manage a data coherency among the plurality of first memory devices.

12. The memory system of claim 11 ,
wherein the coherency manager permits the data coherency to at least one among the plurality of first memory devices in response to a coherency request provided from the at least one first memory device, and
wherein the coherency manager controls the plurality of first memory devices to exchange a coherency information with one another.

13. The memory system of claim 10 , wherein the second memory controller includes:
a handshaking interface configured to transfer the signal between the second memory device and the corresponding processor; and
a register configured to temporarily store data read out from the second memory.

14. The memory system of claim 10 , wherein the data request signal includes a command and an address for the second memory device.

15. The memory system of claim 10 ,
wherein the second memory controller includes a storage unit, and
wherein the second memory controller reads data from the second memory and temporarily stores the read data in the storage unit in response to the data request signal.

16. The memory system of claim 15 , wherein the second memory controller provides the data ready signal to the corresponding processor when the second memory controller temporarily stores the read data in the storage unit in response to the data request signal.

17. The memory system of claim 16 , wherein the corresponding processor provides the second memory controller with the session start signal to receive the read data temporarily stored in the storage unit in response to the data ready signal.

18. The memory system of claim 10 , wherein the second memory device is a nonvolatile memory device.

Assignees

• Sk Hynix Inc

Inventors

• Kim Chang-Hyun
• Kim Min-Chang
• Lee Do-Yun
• Lee Yong-Woo
• Lee Jae-Jin
• Jung Hoe-Kwon

Classifications

• G06F13/1615 Primary

  using a concurrent pipeline structrure · CPC title

• G06F3/0611 Primary

  in relation to response time · CPC title

• G06F2206/1014

  One time programmable [OTP] memory, e.g. PROM, WORM · CPC title

• G06F3/065

  Replication mechanisms · CPC title

• G06F13/1657

  Access to multiple memories · CPC title