Memory interface control

Patent metadata

Field	Value
Publication number	US-9672153-B2
Application number	US-201113067602-A
Country	US
Kind code	B2
Filing date	Jun 13, 2011
Priority date	Jun 13, 2011
Publication date	Jun 6, 2017
Grant date	Jun 6, 2017

Abstract

A memory interface apparatus 24 is provided with first interface circuitry 28 , second interface circuitry 30 and transaction control circuitry 32 . The first interface circuitry receives a first write request from a transaction master 20, 22 and issues a further transaction request associated with the memory address of the first write request via the second interface circuitry to a memory system. When an indication of the completion of the further transaction has been received at the second interface circuitry, then a second write request may be issued from the second interface circuitry to the memory system to write the target data associated with the first write request. After a write response signal in respect of the second write request is received at the second interface circuitry, then an acknowledge signal RACK indicating completion of the further transaction and that the write response signal has been received may be issued from the second interface circuitry. Between issue of the further transaction and issue of the acknowledge signal snoop requests to the memory addresses concerned that arise elsewhere within the memory system may be managed and blocked.

First claim

We claim:

1. Memory interface apparatus comprising:
first interface circuitry configured to connect to transaction master circuitry;
second interface circuitry configured to connect to a memory system; and
transaction control circuitry coupled to said first interface circuitry and said second interface circuitry and configured to:
receive from said transaction master circuitry via said first interface circuitry a first write request to write target data associated with a memory address within said memory system;
issue via said second interface circuitry a further transaction request associated with said memory address;
receive via said second interface circuitry an indication of completion of said further transaction request;
issue via said second interface circuitry a second write request to write at least said write target data to said memory system;
receive via said second interface circuitry a write response signal indicating said write target data has been written to said memory system; and
in dependence upon receipt of said write response signal, issue an acknowledge signal via said second interface circuitry to said memory system indicating said indication of completion associated with said further transaction request and said write response signal have been received.

2. Memory interface apparatus as claimed in claim 1 , wherein said further transaction request is a read request to read current data associated with said memory address from said memory system.

3. Memory interface apparatus as claimed in claim 2 , wherein said indication of completion is a read response signal indicating said current data has been supplied to said memory interface apparatus via said second interface circuitry.

4. Memory interface apparatus as claimed in claim 2 , comprising data storage circuitry, wherein:
said transaction control circuitry is configured to:
form updated data from said current data and said write target data; and
store at least some of said updated data within said data storage circuitry; and

said second write request writes said updated data to said memory system.

5. Memory interface apparatus as claimed in claim 4 , wherein said data storage circuitry is a cache memory configured to store at least one line of cache data including said target write data.

6. Memory interface apparatus as claimed in claim 1 , wherein:
said further transaction request is an invalidate request to invalidate current data associated with said memory address and stored within said memory system; and
said indication of completion is an invalidation completion signal indicating said current data has been invalidated.

7. Memory interface apparatus as claimed in claim 1 , wherein said memory system is a coherent memory system comprising: a main memory;
at least one cache memory configured to store local copies of data;
interconnect circuitry configured to connect said main memory and said at least one cache memory; and
coherency control circuitry configured to control data coherency between data stored within said main memory and said at least one cache memory using snoop request signals.

8. Memory interface apparatus as claimed in claim 7 , wherein:
said further transaction request is a read request to read current data associated with said memory address from said memory system; and
said indication of completion includes an indication that said current data is not stored in any of said at least one cache memory and that said current data is not supplied to said second interface circuitry.

9. Memory interface apparatus as claimed in claim 7 , wherein
said further transaction request is a read request to read current data associated with said memory address from said memory system; and
said indication of completion includes an indication that that none of said at least one cache memory is storing said current data as dirty data having a value different from corresponding data stored within said main memory, any copy of said data has been marked as invalid and that said current data is not supplied to said second interface circuitry.

10. Memory interface apparatus as claimed in claim 7 , wherein said coherency control circuitry is configured to detect said further transaction request issued to said memory system via said second interface circuitry and to stall any transaction requests later within a serialization order managed by said coherency control circuitry within said memory system to said memory address until said acknowledge signal is received from said memory interface apparatus via said second interface circuitry.

11. Memory interface apparatus as claimed in claim 7 , wherein said memory interface apparatus is part of said interconnect circuitry and said first interface circuitry is an interface between said interconnect circuitry and said transaction master circuitry.

12. Memory interface apparatus as claimed in claim 7 , wherein no snoop request signals pass across said second interface circuitry.

13. Memory interface apparatus as claimed in claim 7 , wherein said second write request is processed by said memory system without any dependence upon said acknowledge signal.

14. Memory interface apparatus as claimed in claim 1 , comprising at least one further memory interface configured to connect to further transaction master circuitry.

15. Memory interface apparatus as claimed in claim 1 , wherein said second write request is processed by said memory system without any dependence upon said acknowledge signal.

16. Apparatus for processing data comprising:
a main memory;
at least one cache memory configured to store local copies of data stored within said main memory;
interconnect circuitry configured to connect said main memory and said at least one cache memory;
coherency control circuitry configured to control data coherency between data stored within said main memory and said at least one cache memory using snoop request signals; and
memory interface apparatus having:
first interface circuitry configured to connect to transaction master circuitry;
second interface circuitry configured to connect to said interconnect circuitry; and
transaction control circuitry coupled to said first interface circuitry and said second interface circuitry and configured to:
receive from said transaction master circuitry via said first interface circuitry a first write request to write target data associated with a memory address within at least one of said main memory and said at least one cache memory;
issue via said second interface circuitry a further transaction request associated with said memory address;
receive via said second interface circuitry an indication of completion of said further transaction request;
issue via said second interface circuitry a second write request to write at least said write target data;
receive via said second interface circuitry a write response signal indicating said write target data has been written; and
in dependence upon receipt of said write response signal, issue an acknowledge signal via said second interface circuitry to said coherency control circuitry indicating said indication of completion associated with said further transaction request and said write response signal have been received.

17. Apparatus as claimed in claim 16 , wherein said further transaction request is a read request to read current data associated with said memory address from said memory system.

18. Apparatus as claimed in claim 16 , wherein:
said further transaction request is an invalidate request to invalidate cur

Assignees

• Laycock Christopher William
• Harris Antony John
• Laughton Arthur
• Advanced Risc Mach Ltd

Inventors

• Laycock Christopher William
• Harris Antony John
• Laughton Arthur

Classifications

• G06F12/0835 Primary

  for main memory peripheral accesses (e.g. I/O or DMA) · CPC title

• G06F12/0833

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title