Fan-out semiconductor package

Patent metadata

Field	Value
Publication number	US-10177103-B1
Application number	US-201715807075-A
Country	US
Kind code	B1
Filing date	Nov 8, 2017
Priority date	Jul 4, 2017
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

A fan-out semiconductor package includes: a support member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the support member and the semiconductor chip; and a connection member disposed on the support member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The support member includes a glass plate and an insulating layer connected to the glass plate.

First claim

What is claimed is:

1. A fan-out semiconductor package comprising:
a support member having a through-hole;
a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface;
an encapsulant encapsulating at least portions of the support member and the semiconductor chip; and
a connection member disposed on the support member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads,
wherein the support member includes a glass plate and an insulating layer connected to the glass plate.

2. The fan-out semiconductor package of claim 1 , wherein the glass plate is an amorphous solid material including a glass component.

3. The fan-out semiconductor package of claim 1 , wherein the insulating layer is formed of an insulating material including an insulating resin and an inorganic filler.

4. The fan-out semiconductor package of claim 1 , wherein the support member includes a redistribution layer electrically connected to the connection pads.

5. The fan-out semiconductor package of claim 4 , wherein the support member further includes vias penetrating through at least one of the glass plate and the insulating layer and electrically connected to the redistribution layer.

6. The fan-out semiconductor package of claim 1 , wherein the insulating layer is disposed on the glass plate, and
the through-hole penetrates through the glass plate and the insulating layer.

7. The fan-out semiconductor package of claim 6 , wherein the insulating layer includes a first insulating layer disposed on a lower surface of the glass plate and a second insulating layer disposed on an upper surface of the glass plate, and
the glass plate has a thickness greater than that of each of the first and second insulating layers.

8. The fan-out semiconductor package of claim 7 , wherein the support member includes the glass plate, a first redistribution layer disposed on the lower surface of the glass plate, a second redistribution layer disposed on the upper surface of the glass plate, the first insulating layer disposed on the lower surface of the glass plate and covering the first redistribution layer, a third redistribution layer disposed on a lower surface of the first insulating layer, a second insulating layer disposed on the upper surface of the glass plate and covering the second redistribution layer, and a fourth redistribution layer disposed on an upper surface of the second insulating layer, and
the first to fourth redistribution layers are electrically connected to the connection pads.

9. The fan-out semiconductor package of claim 8 , wherein the support member includes first vias penetrating through the glass plate and electrically connecting the first and second redistribution layers to each other, second vias penetrating through the first insulating layer and electrically connecting the first and third redistribution layers to each other, and third vias penetrating through the second insulating layer and electrically connecting the second and fourth redistribution layers to each other, and
the first to third vias have different cross-sectional shapes.

10. The fan-out semiconductor package of claim 1 , wherein the insulating layer is disposed to surround outer surfaces of the glass plate, and
the through-hole is formed in the glass plate.

11. The fan-out semiconductor package of claim 10 , wherein the glass plate is not exposed externally of the fan-out semiconductor package.

12. The fan-out semiconductor package of claim 10 , wherein the glass plate has a width greater than that of the insulating layer.

13. The fan-out semiconductor package of claim 10 , wherein the support member includes the glass plate, the insulating layer, a first redistribution layer disposed on a lower surface of the insulating layer, and a second redistribution layer disposed on an upper surface of the insulating layer,
the first and second redistribution layers are electrically connected to the connection pads, and
the glass plate is not in direct contact with any redistribution layers.

14. The fan-out semiconductor package of claim 13 , wherein the support member further includes first vias penetrating through the insulating layer and electrically connecting the first and second redistribution layers to each other, and
no vias are formed in the glass plate.

15. The fan-out semiconductor package of claim 10 , wherein the support member includes the glass plate, a first redistribution layer disposed on a lower surface of the glass plate, a second redistribution layer disposed on an upper surface of the glass plate, the insulating layer, a third redistribution layer disposed on a lower surface of the insulating layer, and a fourth redistribution layer disposed on an upper surface of the insulating layer, and
the first to fourth redistribution layers are electrically connected to the connection pads.

16. The fan-out semiconductor package of claim 15 , wherein the support member further includes first vias penetrating through the glass plate and electrically connecting the first and second redistribution layers to each other and second vias penetrating through the insulating layer and electrically connecting the third and fourth redistribution layers to each other, and
the first and second vias are disposed on levels corresponding to each other.

17. The fan-out semiconductor package of claim 1 , further comprising a passive component disposed side by side with the semiconductor chip in the through-hole.

Assignees

• Samsung Electro Mech

Inventors

• Yi Moon Hee
• Baek Yong Ho
• Kim Tae Seong

Classifications

• H10W90/722

  between stacked chips · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title