Methods for forming a semiconductor device and semiconductor devices

Patent metadata

Field	Value
Publication number	US-10177033-B2
Application number	US-201715629165-A
Country	US
Kind code	B2
Filing date	Jun 21, 2017
Priority date	Jun 21, 2016
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

A method for forming a semiconductor device includes forming a plurality of non-semiconductor material portions at a first side of a semiconductor substrate; forming semiconductor material on the plurality of non-semiconductor material portions to bury the plurality of non-semiconductor material portions within semiconductor material; removing at least a portion of the semiconductor substrate from a second side of the semiconductor substrate to uncover the plurality of non-semiconductor material portions at a backside of the semiconductor device; and forming a rough surface at the backside of the semiconductor device by removing at least a subset of the plurality of non-semiconductor material portions while at least a part of a semiconductor material located laterally between the plurality of non-semiconductor material portions remains or by removing at least a part of a semiconductor material located laterally between the plurality of non-semiconductor material portions while the plurality of non-semiconductor material portions remain.

First claim

What is claimed is:

1. A method for forming a semiconductor device, the method comprising:
forming a plurality of non-semiconductor material portions at a first side of a semiconductor substrate;
forming semiconductor material on the plurality of non-semiconductor material portions to bury the plurality of non-semiconductor material portions within semiconductor material;
removing at least a portion of the semiconductor substrate from a second side of the semiconductor substrate to uncover the plurality of non-semiconductor material portions at a backside of the semiconductor device;
forming a rough surface at the backside of the semiconductor device by
forming a mask layer at an edge termination region at the backside of the semiconductor substrate, and
after forming the mask layer, removing at least a subset of the plurality of non-semiconductor material portions while at least a part of a semiconductor material located laterally between the plurality of non-semiconductor material portions remains or by removing at least a part of a semiconductor material located laterally between the plurality of non-semiconductor material portions while the plurality of non-semiconductor material portions remain, wherein the subset of the plurality of non-semiconductor material portions are removed at regions uncovered by the mask layer; and

forming a backside metallization structure at the rough surface.

2. The method according to claim 1 , wherein the plurality of non-semiconductor material portions comprise a vertical dimension of more than 200 nm.

3. The method according to claim 1 , wherein the plurality of non-semiconductor material portions comprise a vertical dimension of less than 5 μm.

4. The method according to claim 1 , wherein the plurality of non-semiconductor material portions comprise a lateral width of more than 100 nm.

5. The method according to claim 1 , wherein the plurality of non-semiconductor material portions comprise a lateral width of less than 3 μm.

6. The method according to claim 1 , wherein a lateral distance between neighboring non-semiconductor material portions of the plurality of non-semiconductor material portions along at least one lateral direction is larger than 100 nm.

7. The method according to claim 1 , wherein a lateral distance between neighboring non-semiconductor material portions of the plurality of non-semiconductor material portions along at least one lateral direction is less than 20 μM.

8. The method according to claim 1 , wherein forming the plurality of non-semiconductor material portions comprises forming a plurality of trenches and forming non-semiconductor material within the plurality of trenches or forming a non-semiconductor material layer on the semiconductor substrate and structuring the non-semiconductor material layer.

9. The method according to claim 1 , wherein a thickness of the semiconductor material formed on the plurality of non-semiconductor material portions is larger than 2 μm.

10. The method according to claim 1 , wherein forming semiconductor material on the plurality of non-semiconductor material portions comprises epitaxially growing the semiconductor material so that the plurality of non-semiconductor material portions are buried due to lateral overgrowth.

11. The method according to claim 1 , wherein the non-semiconductor material portions of the plurality of non-semiconductor material portions are arranged in a repetitive pattern.

12. The method according to claim 1 , wherein the plurality of non-semiconductor material portions comprise insulating material.

13. The method according to claim 1 , wherein the plurality of non-semiconductor material portions comprise ternary carbide, ternary nitride or metal.

14. The method according to claim 1 , wherein the backside metallization structure is in contact with the plurality of non-semiconductor material portions.

15. The method according to claim 1 , further comprising forming a plurality of electrical element structures at a surface of the semiconductor material formed on the plurality of non-semiconductor material portions.

16. The method according to claim 1 , further comprising soldering the backside metallization structure to a lead frame or a printed circuit board.

17. The method according to claim 1 , wherein the backside metallization structure entirely covers the backside of the semiconductor device.

18. A method for forming a semiconductor device, the method comprising:
forming a plurality of non-semiconductor material portions at a first side of a semiconductor substrate;
forming semiconductor material on the plurality of non-semiconductor material portions to bury the plurality of non-semiconductor material portions within semiconductor material;
removing at least a portion of the semiconductor substrate from a second side of the semiconductor substrate to uncover the plurality of non-semiconductor material portions at a backside of the semiconductor device;
forming a rough surface at the backside of the semiconductor device by
forming a mask layer at an edge termination region at the backside of the semiconductor substrate, and
after forming the mask layer, removing at least a subset of the plurality of non-semiconductor material portions while at least a part of a semiconductor material located laterally between the plurality of non-semiconductor material portions remains, wherein the subset of the plurality of non-semiconductor material portions are removed at regions uncovered by the mask layer; and

forming a backside metallization structure at the rough surface.

19. The method according to claim 18 , wherein the backside metallization structure entirely covers the backside of the semiconductor device.

Assignees

• Infineon Technologies Ag

Inventors

• Hellmund Oliver
• Irsigler Peter
• Schmidt Sebastian
• Schulze Hans-Joachim
• Seider-Schmidt Martina

Classifications

• H10P14/2921

  being crystalline insulating materials · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/9415

  relative to the surface, e.g. recessed, protruding · CPC title

• H10W72/934

  Cross-sectional shape, i.e. in side view · CPC title