Peripheral component interconnect express (PCIE) card having multiple PCIE connectors

Patent metadata

Field	Value
Publication number	US-10176143-B2
Application number	US-201715621825-A
Country	US
Kind code	B2
Filing date	Jun 13, 2017
Priority date	Dec 12, 2014
Publication date	Jan 8, 2019
Grant date	Jan 8, 2019

Abstract

Some embodiments include apparatus and methods having a circuit board, a device located on the circuit board, a first Peripheral Component Interconnect Express (PCIe) connector located on the circuit board and coupled to the device, and a second PCIe connector located on the circuit board and coupled to the device. The first PCIe connector is arranged to couple to a first connector of an additional circuit board. The second PCIe connector is arranged to couple to a second connector of the additional circuit board.

First claim

What is claimed is:

1. An apparatus comprising a semiconductor chip comprising:
a multicore processor;
a network interface controller (NIC);
a first connector to couple to a first Peripheral Component Interconnect Express (PCIe) connector of one or more devices;
a second connector to couple to a second PCIe connector of one or more devices;
a third connector to couple to an InfiniBand network; and
a fourth connector to couple to an Ethernet network.

2. The apparatus of claim 1 , wherein the first connector comprises a first set of conductors and the second connector comprises a second set of conductors.

3. The apparatus of claim 2 , wherein the first and second sets of conductors are arranged based on PCIe connector pin-out specification.

4. A system comprising:
one or more devices comprising a first Peripheral Component Interconnect Express (PCIe) connector;
a chip comprising:
a multicore processor;
a network interface controller (NIC);
a first connector to couple to the first PCIe connector;
a second connector to couple to a second PCIe connector;
a third connector to couple to an InfiniBand network; and

a fourth connector to couple to an Ethernet network.

5. The system of claim 4 , wherein the first connector comprises a first set of conductors and the second connector comprises a second set of conductors.

6. The system of claim 5 , wherein the first and second sets of conductors are arranged based on PCIe connector pin-out specification.

Assignees

• Intel Corp

Inventors

• Tamarkin Vladimir
• Genetti Wayne
• Schweitzer David

Classifications

• G06F13/4221 Primary

  being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus · CPC title

• G06F1/185

  Mounting of expansion boards · CPC title

• H05K1/0296

  Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295 (H05K1/11 takes precedence; lay-out adapted to mounted component configuration H05K1/18) · CPC title

• H01R12/716

  Coupling device provided on the PCB · CPC title

• H05K5/0286

  Receptacles therefor, e.g. card slots, module sockets, card groundings · CPC title