Optimized CMOS analog switch

Patent metadata

Field	Value
Publication number	US-10171072-B2
Application number	US-201615265341-A
Country	US
Kind code	B2
Filing date	Sep 14, 2016
Priority date	Oct 8, 2015
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

An improved analog switch for use in an ultrasound elastography probe is disclosed. The improved analog switch results in less heat dissipation compared to prior art analog switches.

First claim

What is claimed is:

1. An analog switch, comprising:
a first butterfly circuit comprising a first thin gate oxide NMOS transistor in series with a second thin gate oxide NMOS transistor, the first butterfly circuit comprising a first terminal and a second terminal, the second terminal directly coupled to a high voltage source;
a second butterfly circuit comprising a third thin gate oxide NMOS transistor in series with a fourth thin gate oxide NMOS transistor, the second butterfly circuit comprising a third terminal directly coupled to the second terminal and a fourth terminal directly coupled to ground.

2. The switch of claim 1 , wherein the on-resistance of the switch is less than 8 Ohms.

3. The switch of claim 1 , wherein the parasitic capacitance of the switch is less than 10 picoFarads.

4. The switch of claim 1 , wherein the high voltage source comprises a peak-to-peak amplitude greater than 200 volts.

5. The switch of claim 1 , wherein the first butterfly circuit requires power supply voltages in a range between −6 volts and +6 volts.

6. The switch of claim 5 , wherein the second butterfly circuit requires power supply voltages in a range between −6 volts and +6 volts.

7. An analog switch, comprising:
a conducting means for connecting a high voltage source to a transceiver; and
a shunting means for shunting current from a terminal of the conducting means to ground;
wherein the on-resistance of the switch is less than 8 Ohms.

8. An analog switch, comprising:
a conducting means for connecting a high voltage source to a transceiver; and
a shunting means for shunting current from a terminal of the conducting means to ground;
wherein the parasitic capacitance of the switch is less than 10 picoFarads.

Assignees

• Microchip Tech Inc

Inventors

• Ko Isaac
• Ho Ka Wai
• Chan Wan Tim

Classifications

• H03K17/693

  Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors (logic circuits H03K19/00; code converters H03M5/00, H03M7/00) · CPC title

• A61B8/485

  involving measuring strain or elastic properties · CPC title

• H03K17/6874 Primary

  in a symmetrical configuration · CPC title

• A61B8/469

  for selection of a region of interest · CPC title

• H03K17/161 Primary

  in field-effect transistor switches · CPC title