Vertical transport field effect transistors

Patent metadata

Field	Value
Publication number	US-10170617-B2
Application number	US-201715424379-A
Country	US
Kind code	B2
Filing date	Feb 3, 2017
Priority date	Feb 3, 2017
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

The present disclosure relates to semiconductor structures and, more particularly, to vertical transport field effect transistor devices and methods of manufacture. A structure includes: a vertical fin structure having a lower dopant region, an upper dopant region and a channel region between the lower dopant region and the upper dopant region; and a doped semiconductor material provided on sides of the vertical fin structure at a lower portion. The lower dopant region being composed of the doped semiconductor material which is merged into the vertical fin structure at the lower portion.

First claim

What is claimed:

1. A structure, comprising:
a vertical fin structure composed of semiconductor material and having a lower dopant region at a lower portion of the vertical fin structure, an upper dopant region at an upper portion of the vertical fin structure and a channel region between the lower dopant region and the upper dopant region;
a recessed portion in the semiconductor material adjacent to the lower dopant region at a lower portion of the vertical fin structure;
shallow trench isolation structures formed in the semiconductor material, adjacent to the recessed portion; and
doped semiconductor material in the recessed portion in the semiconductor material on sides of the vertical fin structure at the lower portion and adjacent to the shallow trench isolation structures, the lower dopant region being composed of the doped semiconductor material at the lower portion,
wherein the doped semiconductor material comprises a tri-layer of material within the recessed portion, with a higher doped semiconductor material in a lower portion and upper portion of the recessed portion, and a lower doped semiconductor material sandwiched therebetween.

2. The structure of claim 1 , wherein the lower dopant region is a source region or a drain region.

3. The structure of claim 1 , wherein the doped semiconductor material is an epitaxially grown doped semiconductor material that merges into the lower portion of the vertical fin structure, the doped semiconductor material is Si:As, Si:P or Si:CP for an NFET device and Si:B, Si:Ga, SiGe:B, or SiGe:Ga for a PFET device.

4. The structure of claim 3 , wherein the doped semiconductor material has a uniform dopant concentration.

5. The structure of claim 3 , wherein the doped semiconductor material has a dopant gradient concentration, with a lower dopant concentration at a bottom and sidewall of the semiconductor material in the recessed portion and a higher dopant concentration at a top and away from the sidewall of the recessed portion.

6. The structure of claim 1 , wherein the lower doped semiconductor material extends on the sidewall of the recessed portion, nearest to the channel region of the vertical fin structure.

7. The structure of claim 3 , wherein the doped semiconductor material provided in the recessed portion and along its sidewall nearest to the channel region has a higher band gap than the doped semiconductor material in remaining portions of the recess.

8. The structure of claim 1 , wherein the vertical fin structure is composed of the doped semiconductor material, undoped layer of semiconductor material on the doped semiconductor material, a marking layer on the undoped layer of semiconductor material and an undoped layer of semiconductor material on marking layer.

9. The structure of claim 1 , wherein:
the vertical fin structure is a vertical gate structure composed of the semiconductor material,
the upper dopant region is provided in the semiconductor material at the upper portion of the vertical gate structure,
the lower dopant region is provided in the semiconductor material at the lower portion of the vertical gate structure, which comprises dopant of doped epitaxial material provided in the recessed portion of the semiconductor material, and
the channel region is provided in an undoped portion of the semiconductor material of the vertical gate structure between the upper dopant region and the lower dopant region.

10. A structure, comprising:
a vertical fin structure composed of semiconductor material, and comprising a lower dopant region at a lower portion of the vertical fin structure, an upper dopant region at an upper portion of the vertical fin structure and a channel region between the lower dopant region and the upper dopant region;
a recessed portion in the semiconductor material directly on sidewalls of the vertical fin structure at the lower dopant region; and
a doped material in the recessed portion directly on the sidewalls of the vertical fin structure, the lower dopant region being composed of a same dopant of the doped material at the lower portion of the vertical fin structure,
wherein the doped semiconductor material has a tri-layer of material within the recessed portion, with a higher doped semiconductor material in a lower portion and upper portion of the recessed portion, and a lower doped semiconductor material sandwiched therebetween, which extends on the sidewall of the recessed portion, nearest to a channel region of the vertical fin structure.

11. The structure of claim 10 , wherein the doped semiconductor material is an epitaxially grown doped semiconductor material composed of Si:As, Si:P or Si:CP for an NFET device and Si:B, Si:Ga, SiGe:B, or SiGe:Ga for a PFET device.

12. The structure of claim 10 , wherein the doped semiconductor material has a uniform dopant concentration.

13. The structure of claim 10 , wherein the doped semiconductor material has a dopant gradient concentration, with a lower dopant concentration at a bottom and sidewall of the recess at the semiconductor material and a higher dopant concentration at a top and away from the sidewall of the recess.

14. The structure of claim 10 , wherein the vertical fin structure is composed of the doped semiconductor material, undoped layer of semiconductor material on the doped semiconductor material, a marking layer on the undoped layer of semiconductor material and an undoped layer of semiconductor material on marking layer.

15. The structure of claim 10 , wherein:
the vertical fin structure is a vertical gate structure composed of the semiconductor material,
the dopant region at the upper portion is provided in the semiconductor material,
the dopant region at the lower portion is provided in the semiconductor material, which is dopant from doped epitaxial material provided in the recessed portion of the semiconductor material, and
a channel region is provided in an undoped portion of the semiconductor material of the vertical gate structure between the dopant region at the upper portion and the dopant region at the lower portion of the vertical gate structure.

Assignees

• Globalfoundries Inc
• Globalfoundries

Inventors

• Kim Jiseok
• Niimi Hiroaki
• Kim Hoon
• Suvarna Puneet Harischandra
• Bentley Steven
• Fronheiser Jody A

Classifications

• H01L29/1095

  Electricity · mapped topic

• H01L29/66666

  Electricity · mapped topic

• H01L29/7848

  Electricity · mapped topic

• H01L29/7827 Primary

  Electricity · mapped topic

• H01L29/36

  Electricity · mapped topic