Integrated capacitors with nanosheet transistors

Patent metadata

Field	Value
Publication number	US-10170548-B2
Application number	US-201815927441-A
Country	US
Kind code	B2
Filing date	Mar 21, 2018
Priority date	Jun 30, 2016
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

A semiconductor device and process of making the same generally includes simultaneously forming nanosheet capacitors with nanosheet FET devices on the same substrate. The nanosheets in the capacitor have a width and are coupled to one another by sacrificial layers, wherein the sacrificial layers have a width smaller than the nanosheet width, and wherein the nanosheets and the sacrificial layers are conductively coupled to the substrate. The nanosheets in the FET devices are spaced apart and free of sacrificial layers. The nanosheets in the FET device have a width less than half the width of the nanosheets in the capacitor region.

First claim

What is claimed is:

1. A method of making a semiconductor device, the method comprising:
depositing alternating nanosheet layers and sacrificial layers onto a substrate;
simultaneously forming fins in a capacitor region and fins in a device region, wherein the fins in the capacitor region have a greater width than the fins in the device region;
selectively etching the sacrificial layers to form an undercut in the capacitor region and complete removal in the device region;
doping the alternating nanosheet layers and undercut sacrificial layers in the capacitor region, and portions of the substrate underlying the capacitor region;
depositing a high k dielectric layer onto the alternating nanosheet layers and undercut sacrificial layers in the capacitor region, and portions of the substrate underlying the capacitor region, and on the nanosheet layers in the device region; and
forming top and bottom electrodes in the capacitor region.

2. The method of claim 1 , wherein depositing the alternating nanosheet layers and sacrificial layers onto the substrate comprises growing silicon layers as the nanosheet layer and silicon-germanium layers as the sacrificial layers.

3. The method of claim 1 , wherein forming the fins in the capacitor region and in the device region comprises a sidewall image transfer process.

4. The method of claim 1 , wherein selectively etching the sacrificial layers to form the undercut in the capacitor region and complete removal in the device region comprises an isotropic etch process.

5. The method of claim 1 , wherein simultaneously forming fins in the capacitor region and fins in the device region comprises providing the alternating nanosheet layers and sacrificial layers with a width of 25 nanometers to 75 nanometers in the capacitor region and a width of the fins in the device region of at least half of the width in the capacitor region.

6. The method of claim 1 , wherein doping the alternating nanosheet layers and undercut sacrificial layers in the capacitor region, and portions of the substrate underlying the capacitor region comprises forming a block mask over the device region prior to doping to prevent doping in the device region.

7. The method of claim 1 , wherein the nanosheet layers and the sacrificial layers have a thickness from 3 to 30 nanometers.

8. The method of claim 1 , wherein the high k dielectric comprises hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

9. The method of claim 1 , wherein selectively etching the sacrificial layers to form the undercut in the capacitor region and complete removal in the device region comprises a wet etching process.

10. The method of claim 9 , wherein the wet etch process comprises exposing the substrate to buffered hydrofluoric acid (BHF), hydrofluoric acid (HF), hydrofluoric nitric acid (HNA), phosphoric acid, HF diluted by ethylene glycol (HFEG), hydrochloric acid (HCl), or any combination thereof.

11. The method of claim 1 , wherein the high k dielectric layer has a k value ranging from 10 to 30.

12. A method of making a semiconductor device, the method comprising:
depositing a film stack onto a silicon substrate, the film stack comprising alternating layers of silicon and silicon-germanium;
simultaneously defining a capacitor region by forming fins in the film stack having a first width and a device region by forming fins in the film stack having a second width;
isotropically etching the silicon-germanium to form an undercut in the capacitor region and complete removal in the device region, wherein the second width of the film stack in the device region is at least less than half of the first width of the film stack in the capacitor region such that isotropic etching forms the undercut in the capacitor region and complete removal in the device region;
doping the nanosheet, sacrificial layers, and portions of the substrate underlying the capacitor region;
depositing a high k dielectric layer onto the nanosheet, sacrificial layers, and portions of the substrate underlying the capacitor region, and on the nanosheet layers in the device region; and
forming top and bottom electrodes in the capacitor region.

13. The method of claim 12 , wherein doping the nanosheet, sacrificial layers, and portions of the substrate underlying the capacitor region comprises forming a block mask over the device region prior to doping.

14. The method of claim 12 , wherein the nanosheet layers and the sacrificial layers have a thickness from 3 to 30 nanometers.

15. The method of claim 12 , wherein the high k dielectric comprises hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

16. The method of claim 12 , wherein each one of the nanosheets has a thickness equal to each one of the sacrificial layers.

17. The method of claim 12 , wherein the nanosheets in the capacitor region have a width of 25 to 75 nanometers.

18. The method of claim 12 , wherein the high k dielectric layer has a k value ranging from 10 to 30.

19. The method of claim 12 , wherein isotropically etching the silicon-germanium to form an undercut in the capacitor region and complete removal in the device region comprises exposing the substrate to buffered hydrofluoric acid (BHF), hydrofluoric acid (HF), hydrofluoric nitric acid (HNA), phosphoric acid, HF diluted by ethylene glycol (HFEG), hydrochloric acid (HCl), or any combination thereof.

20. The method of claim 12 , wherein isotropically etching the silicon-germanium to form an undercut in the capacitor region and complete removal in the device region comprises reactive ion etching.

Assignees

• IBM

Inventors

• Cheng Kangguo
• Demarest James J
• Gaudiello John G
• Li Juntao

Classifications

• H10P50/283

  by chemical means · CPC title

• H10P14/6939

  characterised by the metal · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H01L21/31111

  Electricity · mapped topic

• H01L29/161

  Electricity · mapped topic