Electronic device and methods of providing and using electronic device

US10170407B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10170407-B2
Application numberUS-201715590843-A
CountryUS
Kind codeB2
Filing dateMay 9, 2017
Priority dateDec 22, 2014
Publication dateJan 1, 2019
Grant dateJan 1, 2019

How to read this patent

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  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Some embodiments include a method of providing an electronic device. The method can comprise: providing a first device substrate; providing one or more first active sections over a second side of the first device substrate at a first device portion of the first device substrate; and after providing the first active section(s) over the second side of the first device substrate at the first device portion, folding a first perimeter portion of the first device substrate toward the first device portion at a first side of the first device substrate so that a first edge portion remains to at least partially frame the first device portion. The first edge portion can comprise a first edge portion width dimension smaller than a first smallest cross dimension of one or more pixel(s) of one or more semiconductor device(s) of the first active section(s). Other embodiments of related methods and devices are also disclosed.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of providing an electronic device, the method comprising: providing a first device substrate comprising a first side and a second side opposite the first side, the first device substrate comprising a first flexible substrate, a first device portion, and a first perimeter portion at least partially framing the first device portion; providing one or more first active sections over the second side of the first device substrate at the first device portion, each first active section of the one or more first active sections comprising at least one first semiconductor device, each first semiconductor device of the at least one first semiconductor device comprising at least one first pixel, and each first pixel of the at least one first pixel comprising a first smallest cross dimension; and after providing the one or more first active sections over the second side of the first device substrate at the first device portion, folding the first perimeter portion of the first device substrate toward the first device portion at the first side of the first device substrate so that a first edge portion remains to at least partially frame the first device portion, the first edge portion comprising a first edge portion width dimension smaller than the first smallest cross dimension; providing a second device substrate comprising a first side and a second side opposite the first side, the second device substrate comprising a second flexible substrate, a second device portion, and a second perimeter portion at least partially framing the second device portion; providing one or more second active sections over the second side of the second device substrate at the second device portion, each second active section of the one or more second active sections comprising at least one second semiconductor device, each second semiconductor device of the at least one second semiconductor device comprising at least one second pixel, and each second pixel of the at least one second pixel comprising a second smallest cross dimension; after providing the one or more second active sections over the second side of the second device substrate at the second device portion, folding the second perimeter portion of the second device substrate toward the second device portion at the first side of the second device substrate so that a second edge portion remains to at least partially frame the second device portion, the second edge portion comprising a second edge portion width dimension smaller than the second smallest cross dimension; and after folding the first perimeter portion of the first device substrate toward the first device portion at the first side of the first device substrate and after folding the second perimeter portion of the second device substrate toward the second device portion at the first side of the second device substrate, arranging the first device substrate adjacent to the second device substrate in an array grid. 2. The method of claim 1 wherein: arranging the first device substrate adjacent to the second device substrate in the array grid comprises coupling the first device substrate to the second device substrate. 3. The method of claim 1 further comprising: providing one or more first wavy metal interconnects over the second side of the first device substrate; providing one or more second wavy metal interconnects over the second side of the second device substrate; and electrically coupling the first wavy metal interconnects to the second wavy metal interconnects. 4. The method of claim 1 wherein: the first edge portion width dimension is approximately equal to the second edge portion width dimension. 5. The method of claim 1 wherein: the second edge portion width dimension is smaller than the first smallest cross dimension. 6. The method of claim 1 wherein: the first smallest cross dimension is approximately equal to the second smallest cross dimension. 7. The method of claim 1 further comprising: providing a third device substrate comprising a first side and a second side opposite the first side, the third device substrate comprising a third flexible substrate, a third device portion, and a third perimeter portion at least partially framing the third device portion; providing one or more third active sections over the second side of the third device substrate at the third device portion, each third active section of the one or more third active sections comprising at least one third semiconductor device, each third semiconductor device of the at least one third semiconductor device comprising at least one third pixel, and each third pixel of the at least one third pixel comprising a third smallest cross dimension; after providing the one or more third active sections over the second side of the third device substrate at the third device portion, folding the third perimeter portion of the third device substrate toward the third device portion at the first side of the third device substrate so that a third edge portion remains to at least partially frame the third device portion, the third edge portion comprising a third edge portion width dimension smaller than the third smallest cross dimension; and after folding the first perimeter portion of the first device substrate toward the first device portion at the first side of the first device substrate, after folding the second perimeter portion of the second device substrate toward the second device portion at the first side of the second device substrate, and after folding the third perimeter portion of the third device substrate toward the third device portion at the first side of the third device substrate, arranging the third device substrate adjacent to at least one of the first device substrate or the second device substrate in the array grid. 8. The method of claim 7 further comprising: providing one or more first wavy metal interconnects over the second side of the first device substrate; providing one or more second wavy metal interconnects over the second side of the second device substrate; and electrically coupling the first wavy metal interconnects to the second wavy metal interconnects. 9. The method of claim 7 wherein: the first edge portion width dimension is approximately equal to the second edge portion width dimension. 10. The method of claim 7 wherein: the second edge portion width dimension is smaller than the first smallest cross dimension. 11. The method of claim 7 wherein: the first smallest cross dimension is approximately equal to the second smallest cross dimension. 12. A method of providing an electronic device, the method comprising: providing a first device substrate comprising a first side and a second side opposite the first side, the first device substrate comprising a first flexible substrate, a first device portion, and a first perimeter portion at least partially framing the first device portion; providing one or more first active sections over the second side of the first device substrate at the first device portion, each first active section of the one or more first active sections comprising at least one first semiconductor device, each first semiconductor device of the at least one first semiconductor device comprising at least one first pixel, and each first pixel of the at least one first pixel comprising a first smallest cross dimension; and after providing the one or more first active sections over the second side of the first device substrate at the first device portion, folding the first perimeter portion of the first device substrate toward the first device portion at the first side of the first device substrate so that a f

Assignees

Inventors

Classifications

  • Details of sensors specially adapted for in-vivo measurements · CPC title

  • the sensor is mounted in or on a conformable substrate or carrier · CPC title

  • used as a support during build up manufacturing of active devices · CPC title

  • Details of chemical or physical process used for separating the auxiliary support from a device or a wafer · CPC title

  • using temporarily an auxiliary support · CPC title

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Frequently asked questions

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What does patent US10170407B2 cover?
Some embodiments include a method of providing an electronic device. The method can comprise: providing a first device substrate; providing one or more first active sections over a second side of the first device substrate at a first device portion of the first device substrate; and after providing the first active section(s) over the second side of the first device substrate at the first devic…
Who is the assignee on this patent?
Smith Joseph, Howard Emmett, Blain Christen Jennifer, and 2 more
What technology area does this patent fall under?
Primary CPC classification H10W70/688. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).