Technique to deposit metal-containing sidewall passivation for high aspect ratio cylinder etch

US10170323B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10170323-B2
Application numberUS-201715440842-A
CountryUS
Kind codeB2
Filing dateFeb 23, 2017
Priority dateDec 4, 2014
Publication dateJan 1, 2019
Grant dateJan 1, 2019

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  1. Title

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  2. Abstract

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  4. Key dates

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  5. First independent claim

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls of the feature to prevent lateral etch of the dielectric material during the etching operations. The protective coating may be deposited using methods that result in formation of the protective coating along substantially the entire length of the sidewalls. The protective coating may be deposited using particular reaction mechanisms that result in substantially complete sidewall coating. Metal-containing coatings have been shown to provide particularly good resistance to lateral etch during the etching operation. In some cases, a bilayer approach may be used to deposit the protective coating on sidewalls of partially etched features.

First claim

Opening claim text (preview).

What is claimed is: 1. A method of etching a feature in a dielectric-containing stack on a substrate, the method comprising: (a) generating a first plasma comprising an etching reactant, exposing the substrate to the first plasma, and partially etching the feature in the dielectric-containing stack; (b) after (a), depositing a protective film on sidewalls of the feature, the protective film comprising a metal, wherein the protective film comprises an electrically conductive film; and (c) repeating (a)-(b) until the feature is etched to a final depth, wherein the protective film deposited in (b) substantially prevents lateral etch of the feature during (a), and wherein the feature has an aspect ratio of about 5 or greater at its final depth. 2. The method of claim 1 , wherein the protective film comprises a metal nitride, a metal carbide, a metal boride, or a combination thereof. 3. The method of claim 1 , wherein the metal in the protective film is selected from the group consisting of titanium, tantalum, ruthenium, aluminum, iron, hafnium, and combinations thereof. 4. The method of claim 3 , wherein the metal in the protective film is provided as a metal nitride, a metal carbide, a metal boride, or a combination thereof. 5. The method of claim 4 , wherein the protective film comprises metal nitride. 6. The method of claim 1 , wherein (b) comprises depositing the protective film through an atomic layer deposition reaction comprising: (i) exposing the substrate to a first deposition reactant and allowing the first deposition reactant to adsorb onto the sidewalls of the feature; and (ii) after (i), exposing the substrate to a second deposition reactant and reacting the first and second deposition reactants in a surface reaction, thereby forming the protective film on the sidewalls of the feature. 7. The method of claim 6 , wherein (b) does not involve plasma. 8. The method of claim 6 , wherein (ii) further comprises exposing the substrate to a second plasma comprising the second deposition reactant, wherein exposing the substrate to the second plasma drives a surface reaction between the first deposition reactant and the second deposition reactant, thereby forming the protective film on the sidewalls of the feature. 9. The method of claim 1 , wherein the protective film comprises at least a first sub-layer and a second sub-layer, the first and second sub-layers being deposited under different conditions. 10. The method of claim 9 , wherein the first and second sub-layers have different compositions. 11. The method of claim 9 , wherein the first sub-layer comprises a metal nitride, a metal oxide, a metal carbide, a metal boride, or a combination thereof, and wherein the second sub-layer comprises metal that is substantially in elemental form. 12. The method of claim 1 , wherein at the final depth, the feature has an aspect ratio of about 20 or greater, and a bow of about 20% or less. 13. The method of claim 1 , wherein the feature is formed while forming a VNAND device, and wherein the dielectric-containing stack comprises alternating layers of (i) an oxide material, and (ii) a nitride material or polysilicon material. 14. The method of claim 1 , wherein the feature is formed while forming a DRAM device, and wherein the dielectric-containing stack comprises layers of silicon oxide and one or more layers of silicon nitride. 15. The method of claim 1 , wherein (b) comprises depositing the protective film through a chemical vapor deposition reaction comprising exposing the substrate to a first deposition reactant and a second deposition reactant simultaneously. 16. The method of claim 1 , wherein (a) and (b) are repeated at least one time. 17. The method of claim 1 , wherein the protective film comprises a layer of metal that is substantially in elemental form.

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Classifications

  • by purging residual gases from the reaction chamber or gas lines · CPC title

  • Borides · CPC title

  • Relative arrangement or disposition of electrodes; moving means · CPC title

  • Oxides · CPC title

  • Plural frequencies · CPC title

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What does patent US10170323B2 cover?
Various embodiments herein relate to methods, apparatus and systems for forming a recessed feature in a dielectric-containing stack on a semiconductor substrate. Separate etching and deposition operations are employed in a cyclic manner. Each etching operation partially etches the feature. Each deposition operation forms a protective coating (e.g., a metal-containing coating) on the sidewalls o…
Who is the assignee on this patent?
Lam Res Corp
What technology area does this patent fall under?
Primary CPC classification H10P72/0421. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Jan 01 2019 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).