Integration of photonic, electronic, and sensor devices with SOI VLSI microprocessor technology

Patent metadata

Field	Value
Publication number	US-10168478-B2
Application number	US-201715466966-A
Country	US
Kind code	B2
Filing date	Mar 23, 2017
Priority date	Apr 2, 2014
Publication date	Jan 1, 2019
Grant date	Jan 1, 2019

Abstract

According to an aspect of the present principles, methods are provided for fabricating an integrated structure. A method includes forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure. The method further includes mounting the VLSI structure to a support structure. The method additionally includes removing at least a portion of the semiconductor layer from the VLSI structure. The method also includes attaching an upper layer to the top of the VLSI structure. The upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than the semiconductor layer. The upper layer includes at least one hole for at least one of a photonic device or an electronic device. The method further includes releasing said VLSI structure from the support structure.

First claim

What is claimed is:

1. A method for fabricating an integrated structure comprising:
forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure;
mounting the VLSI structure to a support structure;
removing at least a portion of the semiconductor layer from the VLSI structure;
attaching an upper layer to the top of the VLSI structure, wherein said upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than said semiconductor layer and said upper layer includes a mounting location for at least one of a photonic device or an electronic device; and
releasing said VLSI structure from the support structure.

2. The method of claim 1 , wherein said VLSI structure includes at least one electronic element and at least one photonic element.

3. The method of claim 2 , wherein said VLSI structure includes a dielectric layer that has a thickness of less than 200 nm and is disposed beneath said semiconductor layer.

4. The method of claim 3 , wherein, at said attaching step, one or more of said at least one electronic element or said at least one photonic element is disposed beneath said dielectric layer.

5. The method of claim 1 , further comprising fabricating said upper layer by providing said mounting location as at least one via filled with a conductive material.

6. The method of claim 1 , further comprising forming at least a portion of the electronic device in the upper layer before the upper layer is attached to the top of the VLSI structure.

7. The method of claim 1 , further comprising forming at least a portion of the photonic device and at least a portion of the electronic device in the upper layer.

8. The method of claim 7 , wherein the portion of the electronic device is coupled to an active electronic device.

9. The method of claim 8 , wherein the portion of the electronic device is an antenna.

10. The method of claim 1 , further comprising attaching at least one of an optical fiber or a laser to said mounting location.

11. The method of claim 1 , wherein the material has a transmittance of greater than eighty percent at a particular light wavelength used and a resistivity of at least 10 Ohm.com.

12. The method of claim 1 , further comprising attaching a bottom of said VLSI structure to a wafer.

13. A method for fabricating an integrated structure comprising:
forming a very large scale integration (VLSI) structure including a semiconductor layer at a top of the VLSI structure;
removing at least a portion of the semiconductor layer from the VLSI structure; and
attaching an upper layer to the top of the VLSI structure, wherein said upper layer is primarily composed of a material that has at least one of a higher resistivity or a higher transparency than said semiconductor layer and said upper layer includes a mounting location for at least one of a photonic device or an electronic device.

14. The method of claim 13 , wherein said VLSI structure includes at least one electronic element and at least one photonic element.

15. The method of claim 14 , wherein said VLSI structure includes a dielectric layer that has a thickness of less than 200 nm and is disposed beneath said semiconductor layer.

16. The method of claim 15 , wherein, at said attaching step, one or more of said at least one electronic element or said at least one photonic element is disposed beneath said dielectric layer.

17. The method of claim 13 , further comprising fabricating said upper layer by providing said mounting location as at least one via filled with a conductive material.

18. The method of claim 13 , further comprising forming at least a portion of the electronic device in the upper layer before the upper layer is attached to the top of the VLSI structure.

19. The method of claim 13 , further comprising forming at least a portion of the photonic device and at least a portion of the electronic device in the upper layer.

20. The method of claim 13 , wherein the material has a transmittance of greater than eighty percent at a particular light wavelength used and a resistivity of at least 10 Ohm.com.

Assignees

• IBM

Inventors

• Babakhani Aydin
• Cordes Steven A
• Plouchart Jean-Olivier
• Reynolds Scott K
• Sorce Peter J
• Trzcinski Robert E

Classifications

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title

• H10W72/072

  of bump connectors · CPC title

• H10W72/07307

  the auxiliary member being a temporary substrate, e.g. a removable substrate · CPC title

• H10W72/07323

  Active alignment, e.g. using optical alignment using marks or sensors · CPC title