Methods and apparatuses for signal translation in a buffered memory

Patent metadata

Field	Value
Publication number	US-10164817-B2
Application number	US-201715465421-A
Country	US
Kind code	B2
Filing date	Mar 21, 2017
Priority date	Mar 21, 2017
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

According to one embodiment, A data buffer is described. The data buffer comprises a first input/output circuit configured to receive and provide a first signal encoded according to a first communications protocol, a second input/output circuit configured to receive and provide a second signal encoded according to a second communications protocol, and a conversion circuit coupled to the first and second input/output circuits and configured to convert the first signal to the second signal and to convert the second signal to the first signal.

First claim

What is claimed is:

1. An apparatus comprising:
a first data bus configured to provide a binary signal;
a data buffer coupled to the first data bus, the data buffer configured to receive the binary signal and to convert the binary signal to a multilevel signal, wherein the data buffer comprises:
a binary input/output circuit having a binary transmitter circuit and a binary receiver circuit coupled to the first data bus,
a multilevel input/output circuit having a multilevel transmitter circuit and a multilevel receiver circuit coupled to the second data bus, and
a conversion circuit coupled to the binary input/output circuit and the multilevel input/output circuit, the conversion circuit configured to convert binary signals to multilevel signals and to convert multilevel signals to binary signals, wherein the conversion circuit comprises:
a deserialization circuit comprising a first latch configured to latch a first serial data bit received on the first data bus at a first time and a second latch configured to latch a second serial data bit received on the first data bus at a second time, and
a parallel data synchronization circuit configured to synchronize the first serial data bit and the second data bit to generate first and second parallel data bits, wherein the multilevel transmitter circuit is configured to provide a multilevel signal based on the first and second parallel data bits;

a second data bus coupled to the data buffer configured to provide the multilevel signal;
a memory configured to receive the multilevel signal; and
a timing circuit configured to provide a first clock signal having a first frequency and a second clock signal having a second frequency to the data buffer, wherein the binary signal is received at the data buffer based on the first clock signal and the multilevel signal is provided by the data buffer based on the second clock signal.

2. A method comprising:
receiving, at a data buffer, a binary data signal comprising a plurality of serial data bits;
converting, by the data buffer, the plurality of serial data bits to a plurality of parallel data bits, wherein converting the plurality of serial bits to the plurality of parallel bits comprises:
latching, with a deserialization circuit, a first serial data bit at a first time;
latching, with the deserialization circuit, a second serial data bit at a second time; and
synchronizing, with a parallel data synchronization circuit, the first latched serial data bit and the second latched serial data bit to generate the plurality of parallel data bits;
encoding, by the data buffer, the plurality of parallel data bits in a multilevel signal; and
providing, by the data buffer, the multilevel signal to a memory array.

3. An apparatus comprising:
a first data bus configured to provide a binary signal;
a data buffer coupled to the first data bus, the data buffer configured to receive the binary signal and to convert the binary signal to a multilevel signal;
a second data bus coupled to the data buffer configured to provide the multilevel signal; and
a memory configured to receive the multilevel signal, wherein the data buffer comprises:
a binary input/output circuit having a binary transmitter circuit and a binary receiver circuit coupled to the first data bus,
a multilevel input/output circuit having a multilevel transmitter circuit and a multilevel receiver circuit coupled to the second data bus, and
a conversion circuit coupled to the binary input/output circuit and the multilevel input/output circuit, the conversion circuit configured to convert binary signals to multilevel signals and to convert multilevel signals to binary signals, the conversion circuit comprises:
a deserialization circuit comprising a first latch configured to latch a first serial data bit received on the first data bus at a first time and a second latch configured to latch a second serial data bit received on the first data bus at a second time, and
a parallel data synchronization circuit configured to synchronize the first serial data bit and the second data bit to generate first and second parallel data bits, wherein the multilevel transmitter circuit is configured to provide a multilevel signal based on the first and second parallel data bits.

4. The apparatus of claim 3 , wherein the data buffer is configured to provide the multilevel signal at a lower frequency than the binary signal.

5. The apparatus of claim 3 , wherein the second data bus is less than 2.0 mm.

6. The apparatus of claim 3 , wherein the data buffer is further configured to receive a multilevel signal on the second data bus, to convert the multilevel signal to a binary signal, and to provide the binary signal on the first data bus.

7. The apparatus of claim 3 , wherein the multilevel receiver circuit comprises a multilevel decoder circuit configured to decode multilevel signals and to provide a plurality of parallel data bits.

8. The apparatus of claim 3 , wherein the conversion circuit comprises a serializer circuit configured to serialize the plurality of parallel data bits and to provide a stream of serial data bits to the binary transmitter circuit,
wherein the serializer circuit comprises a first passgate configured to provide a first parallel data bit to the binary transmitter circuit at a first time and to provide a second parallel data bit to the binary transmitter circuit at a second time.

Assignees

• Micron Technology Inc

Inventors

• Hollis Timothy M
• Gans Dean
• Richards Randon
• Schober Bruce W

Classifications

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• H04L47/6225

  Fixed service order, e.g. Round Robin · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• H04L41/0226 Primary

  Mapping or translating multiple network management protocols · CPC title

• G11C2207/101

  Analog or multilevel bus · CPC title