Wave dynamic differential logic

Patent metadata

Field	Value
Publication number	US-8947123-B2
Application number	US-201213691398-A
Country	US
Kind code	B2
Filing date	Nov 30, 2012
Priority date	Feb 13, 2004
Publication date	Feb 3, 2015
Grant date	Feb 3, 2015

Abstract

Wave Dynamic Differential Logic (WDDL) is provided, wherein a differential logic stage is pre-charged or pre-discharged by a previous logic stage, such as, for example, a previous SDDL stage, a WDDL stage, etc. In one embodiment, a Divided Wave Dynamic Differential Logic (DWDDL) is provided wherein a WDDL circuit is conveniently implemented as dual logic trees.

First claim

What is claimed is:

1. A method of operating a logic circuit, comprising:
during a pre-charge phase associated with a logic tree comprising a plurality of interconnected differential logic gates:
receiving a pre-charge wave at at least first and second inputs of a first differential logic gate of the plurality of interconnected differential logic gates;
propagating the pre-charge wave from the first and second inputs of the first differential logic gate to at least first and second outputs of the first differential logic gate;
receiving the pre-charge wave propagated by the first differential logic gate at at least first and second inputs of a second differential logic gate of the plurality of interconnected differential logic gates, the second differential logic gate subsequent to the first differential logic gate in the logic tree;
propagating the received pre-charge wave from the first and second inputs of the second differential logic gate to at least first and second outputs of the second differential logic gate,

wherein the first and second differential logic gates do not include separate pre-charge signal inputs.

2. The method of claim 1 , further comprising, during an evaluation phase associated with the logic tree:
with the first differential logic gate, operating on differential data signals applied to the first and second inputs of the first differential logic gate, wherein the first and second outputs of the first differential logic gate evaluate to first differential values based on a combinatorial logic function implemented by the first differential logic gate, and
with the second differential logic gate, operating on differential data signals applied to the first and second inputs of the second differential logic gate, wherein the first and second outputs of the second differential logic gate evaluate to second differential values based on a combinatorial logic function implemented by the second differential logic gate and based at least in part on the first differential values,
wherein, during the pre-charge phase, the first output of the first differential logic gate is pre-charged to the same value as the second output of the first differential logic gate, and the first output of the second differential logic gate is pre-charged to the same value as the second output of the second differential logic gate.

3. The method of claim 1 , further comprising, with at least one clocked register, passing the pre-charge wave from the first logic tree to a second logic tree comprising a second plurality of interconnected differential logic gates, wherein the at least one clocked register does not include a separate pre-charge input.

4. A method of operating a logic circuit, comprising:
during a pre-discharge phase associated with a logic tree comprising a plurality of interconnected differential logic gates:
receiving a pre-discharge wave at at least first and second inputs of a first differential logic gate of the plurality of interconnected differential logic gates;
propagating the pre-discharge wave from the first and second inputs of the first differential logic gate to at least first and second outputs of the first differential logic gate;
receiving the pre-discharge wave propagated by the first differential logic gate at at least first and second inputs of a second differential logic gate of the plurality of interconnected differential logic gates, the second differential logic gate subsequent to the first differential logic gate in the logic tree;
propagating the received pre-discharge wave from the first and second inputs of the second differential logic gate to at least first and second outputs of the second differential logic gate,

wherein the first and second differential logic gates do not include separate pre-discharge signal inputs.

5. The method of claim 4 , further comprising, during an evaluation phase associated with the logic tree:
with the first differential logic gate, operating on differential data signals applied to the first and second inputs of the first differential logic gate, wherein the first and second outputs of the first differential logic gate evaluate to first differential values based on a combinatorial logic function implemented by the first differential logic gate, and
with the second differential logic gate, operating on differential data signals applied to the first and second inputs of the second differential logic gate, wherein the first and second outputs of the second differential logic gate evaluate to second differential values based on a combinatorial logic function implemented by the second differential logic gate and based at least in part on the first differential values,
wherein, during the pre-charge phase, the first output of the first differential logic gate is pre-discharged to the same value as the second output of the first differential logic gate, and the first output of the second differential logic gate is pre-discharged to the same value as the second output of the second differential logic gate.

6. The method of claim 4 , further comprising, with at least one clocked register, passing the pre-discharge wave from the first logic tree to a second logic tree comprising a second plurality of interconnected differential logic gates, wherein the at least one clocked register does not include a separate pre-discharge input.

7. A logic circuit, comprising:
a logic tree comprising a plurality of interconnected logic gates, the plurality of interconnected differential logic gates comprising:
a first differential logic gate comprising at least first and second inputs and at least first and second outputs, the first differential logic gate configured, during a pre-charge phase associated with the logic tree, to:
receive a pre-charge wave on the first and second inputs of the first differential logic gate; and
propagate the received pre-charge wave to the first and second outputs of the first differential logic gate, wherein the first output of the first differential logic gate is pre-charged to the same value as the second output of the first differential logic gate; and

a second differential logic gate subsequent to the first differential logic gate in the logic tree, comprising at least first and second inputs and at least first and second outputs, and configured, during the pre-charge phase, to:
receive, on the first and second inputs of the second differential logic gate, the pre-charge wave propagated by the first differential logic gate; and
propagate the pre-charge wave to the first and second outputs of the second differential logic gate, wherein the first output of the second differential logic gate is pre-charged to the same value as the second output of the second differential logic gate.

8. The logic circuit of claim 7 , wherein the first and second differential logic gates do not include separate pre-charge signal inputs.

9. The logic circuit of claim 7 , wherein
the first differential logic gate is further configured, during an evaluation phase associated with the logic tree, to operate on differential data signals applied to the first and second inputs of the first differential logic gate, wherein the first and second outputs of the first differential logic gate evaluate to first differential values based on a combinatorial logic function implemented by the first differential logic gate, and
the second differential logic gate is further configured, during the evaluation phase, to operate on differential data signals applied to the first and second inputs of the second differential logic gate, wherein the first and second outputs of the second differential logic gate evaluate to second differential values based on a combinatorial logic functi

Assignees

• Univ California

Inventors

• Verbauwhede Ingrid
• Tiri Kris J V

Classifications

• G06F7/00 Primary

  Methods or arrangements for processing data by operating upon the order or content of the data handled (logic circuits H03K19/00) · CPC title

• H04L2209/125

  Parallelization or pipelining, e.g. for accelerating processing of cryptographic operations · CPC title

• G06F2207/7266

  Hardware adaptation, e.g. dual rail logic; calculate add and double simultaneously · CPC title

• H04L9/003

  for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA] · CPC title

• G06F30/394 Primary

  Routing (G06F30/396 takes precedence) · CPC title