Integrated physical coding sublayer and forward error correction in networking applications

Patent metadata

Field	Value
Publication number	US-10164734-B2
Application number	US-201414445342-A
Country	US
Kind code	B2
Filing date	Jul 29, 2014
Priority date	Jun 30, 2014
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

Method and apparatus for receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer. The method includes performing a first forward error-correcting (FEC) sub-function on the data in the PCS transmit structure. The method further includes transmitting the data on one or more physical medium attachment (PMA) lanes to a PCS receive structure. The method also includes performing a second FEC sub-function on the data in the PCS receive structure.

First claim

What is claimed is:

1. A method comprising:
receiving data at a physical coding sublayer (PCS) transmit structure from a media access control (MAC) sublayer;
encoding, in a first clock domain, the data received from the MAC sublayer into PCS blocks before performing forward error-correction (FEC) encoding on the data;
inserting one or more alignment markers in the data;
performing FEC encoding, in the first clock domain, on the one or more alignment markers and the data in the PCS transmit structure to generate FEC encoded data;
transmitting the FEC encoded data from the first clock domain with a first clock cycle to a second clock domain with a second clock cycle, wherein the first clock cycle is different from the second clock cycle;
transmitting the FEC encoded data on one or more physical medium attachment (PMA) lanes to a PCS receive structure; and
performing FEC decoding, in the second clock domain, on the FEC encoded data in the PCS receive structure to generate FEC decoded data and removing the one or more alignment markers from the FEC decoded data;
decoding, in the second clock domain, the FEC decoded data into MAC blocks, wherein the FEC decoded data is received after FEC decoding is performed on the data.

2. The method of claim 1 , wherein performing the FEC encoding comprises performing Reed-Solomon encoding on the one or more alignment markers and the data.

3. The method of claim 1 , wherein performing the FEC decoding comprises performing Reed-Solomon decoding on the FEC encoded data.

4. The method of claim 1 , wherein performing the FEC encoding comprises performing the FEC encoding on one or more 66-bit PCS blocks.

5. The method of claim 1 , wherein transmitting the FEC encoded data comprises transmitting the FEC encoded data on a high-speed serializer/deserializer.

6. The method of claim 1 , wherein the FEC encoded data is received at the PCS receive structure in one or more plesiochronous input first-in first-outs (FIFOs).

7. The method of claim 1 , wherein the first clock domain comprises a media access control (MAC) Interface (MI) clock domain, and wherein the second clock domain comprises a physical medium attachment (PMA) clock domain.

Assignees

• IBM

Inventors

• Basso Claude
• Song Cheng Wei
• Verplanken Fabrice Jean

Classifications

• H04L1/0045

  Arrangements at the receiver end · CPC title

• H03M13/1515

  Reed-Solomon codes · CPC title

• H03M13/611

  Specific encoding aspects, e.g. encoding by means of decoding · CPC title

• H04L1/0041 Primary

  Arrangements at the transmitter end · CPC title

• H04L25/14

  Channel dividing arrangements {, i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver} · CPC title