Dead time circuit for a switching circuit and a switching amplifier

Patent metadata

Field	Value
Publication number	US-9866188-B2
Application number	US-201515122577-A
Country	US
Kind code	B2
Filing date	Apr 2, 2015
Priority date	Apr 2, 2014
Publication date	Jan 9, 2018
Grant date	Jan 9, 2018

Abstract

A dead time circuit ( 750 ) for a switching circuit is disclosed. The dead-time circuit comprises: an input ( 752 ) for receiving a switching signal of the switching circuit with at least one supply rail having a ground bounce signal; first and second outputs ( 754 a, 754 b ); a first feedforward path ( 756 ) coupled to the first output and arranged to receive the switching signal; a second feedforward path ( 758 ) coupled to the second output and arranged to receive the switching signal; a first feedback path ( 760 ) forming a first feedback loop between the first output and the second feedforward path; and a second feedback path ( 762 ) forming a second feedback loop between the second output and the first feedforward path; wherein each of the first and second feedforward paths includes a respective first and second delay circuit ( 764 a, 764 b ), each having a time delay greater than a predetermined time period of the ground bounce signal. A switching amplifier is also disclosed.

First claim

The invention claimed is:

1. A dead time circuit for a switching circuit, the dead-time circuit comprising:
(i) an input for receiving a switching signal of the switching circuit with at least one supply rail having a ground bounce signal;
(ii) first and second outputs;
(iii) a first feedforward path coupled to the first output and arranged to receive the switching signal;
(iv) a second feedforward path coupled to the second output and arranged to receive the switching signal;
(v) a first feedback path forming a first feedback loop between the first output and the second feedforward path; and
(vi) a second feedback path forming a second feedback loop between the second output and the first feedforward path;
wherein each of the first and second feedforward paths includes a respective first and second delay circuit, each having a time delay greater than a time period of the ground bounce signal determined according to the equation: t=2π(LC)^0.5,
where t is the time period of the ground bounce signal, L is the inductance of a bonding wire and C is the capacitance of the at least one supply rail.

2. The dead time circuit according to claim 1 , wherein the first feedforward path includes a first logic gate for receiving the switching signal and an output signal from the second output via the second feedback path.

3. The dead time circuit according to claim 2 , wherein the second feedback path includes a second logic gate.

4. The dead time circuit according to claim 3 , wherein the second logic gate includes an inverter.

5. The dead time circuit according to claim 2 , wherein the first logic gate's output is coupled to an input of the first delay circuit, and the first delay circuit's output is coupled to a first driver for boosting a first delayed signal from the first delay circuit.

6. The dead time circuit according to claim 1 , wherein the second feedforward path includes a third logic gate for receiving the switching signal and an output signal from the first output via the first feedback path.

7. The dead time circuit according to claim 6 , wherein the first feedback path includes a fourth logic gate.

8. The dead time circuit according to claim 7 , wherein the fourth logic gate includes an inverter or a Level Shifter.

9. The dead time circuit according to claim 6 , wherein the third logic gate's output is coupled to an input of the second delay circuit, and the second delay circuit's output is coupled to a second driver for boosting a second delayed signal from the second delay circuit.

10. The dead time circuit according to claim 1 , wherein the second feedforward path includes third and fourth logic gates, the third logic gate for receiving the switching signal, the fourth logic gate for receiving the third logic gate's output and an output signal from the first output via the first feedback path.

11. The dead time circuit according to claim 10 , wherein the third and fourth logic gates respectively include an inverter and an AND gate.

12. The dead time circuit according to claim 1 , wherein the first feedforward path includes first and second logic gates, the first logic gate for receiving the switching signal, the second logic gate for receiving the first logic gate's output and an output signal from the second output via the second feedback path.

13. The dead time circuit according to claim 12 , wherein the first and second logic gates respectively include an inverter and a NOR gate.

14. A switching circuit for generating a switching signal, the switching circuit comprising:
a loop filter for producing a filtered signal from an input signal;
a modulator for modulating the filtered signal to produce a modulated switching signal; and
an output stage including the dead time circuit according to claim 1 ,

wherein the modulated switching signal is delayed by the first and second delay circuits to generate the switching signal for driving a load.

15. The switching circuit according to claim 14 , wherein the modulator includes a pulse width modulator, bang-bang control modulator, Sigma-Delta modulator or self-oscillation modulator.

16. The switching circuit according to claim 14 in the form of an amplifier or a DC-DC converter.

17. A switching amplifier comprising:
an inner feedback loop; and
an outer feedback loop having a loop gain and comprises a first integrator with at least one zero and a second integrator; wherein the inner feedback loop includes a closed-loop gain comprising the second integrator of the outer feedback loop, the closed-loop gain of the inner feedback loop having at least one pole;
the first integrator having a reactive element configured to generate a zero to at least partially cancel the at least one pole of the closed-loop gain of the inner feedback loop.

18. The switching amplifier according to claim 17 , wherein
the first integrator has three poles and a further zero, and
the closed-loop gain of the inner feedback loop has one zero and a further pole.

19. The switching amplifier according to claim 18 , wherein
the further zero of the first integrator at least partially cancels the further pole of the closed-loop gain of the inner feedback loop.

20. The switching amplifier according to claim 17 , wherein the reactive element emulates an inductor.

21. The switching amplifier according to claim 20 , wherein the inductor includes a transconductance circuit.

22. The switching amplifier according to claim 17 , further comprising a modulator wherein
the second integrator's input is electrically coupled to an output of the first integrator and to an amplifier output for producing an amplified signal, and the second integrator's output is electrically coupled to an input to the modulator, and wherein
the first integrator's input is electrically coupled to the amplifier output.

23. The switching amplifier according to claim 22 , wherein the first integrator's input is also electrically coupled to an amplifier input for receiving a signal to be amplified.

24. The switching amplifier according to claim 22 , further comprising a third feedback loop having a third integrator, the third integrator's input is electrically coupled to an amplifier input for receiving a signal to be amplified, and to the amplifier output.

25. A switching amplifier comprising:
an inner feedback loop;
an outer feedback loop having a loop gain and comprises a first integrator with at least one zero and a second integrator; wherein the inner feedback loop includes a closed-loop gain comprising the second integrator of the outer feedback loop, the closed-loop gain of the inner feedback loop having at least one pole;
the first integrator having a reactive element configured to generate a zero to at least partially cancel the at least one pole of the closed-loop gain of the inner feedback loop; and
an output stage having a dead time circuit wherein the dead time circuit comprises:
(i) an input for receiving a switching signal of a switching circuit with at least one supply rail having a ground bounce signal;
(ii) first and second outputs;
(iii) a first feedforward path coupled to the first output and arranged to receive the switching signal;
(iv) a second feedforward path coupled to the second output and arranged to receive the switching signal;
(v) a first feedback path forming a first feedback loop between the first output and the second feedforward path; and
(vi) a second feedback path

Assignees

• Univ Nanyang Tech

Inventors

• Chang Joseph Sylvester
• Ge Tong
• Guo Linfei

Classifications

• H03F3/217

  Class D power amplifiers; Switching amplifiers · CPC title

• H03F3/2171 Primary

  with field-effect devices (H03F3/2173 - H03F3/2178 take precedence) · CPC title

• H03K17/162

  without feedback from the output circuit to the control circuit · CPC title

• H03F2200/351

  Pulse width modulation being used in an amplifying circuit · CPC title

• H03F3/2173

  of the bridge type · CPC title