On-chip impedance network with digital coarse and analog fine tuning

Patent metadata

Field	Value
Publication number	US-10164633-B2
Application number	US-201715645125-A
Country	US
Kind code	B2
Filing date	Jul 10, 2017
Priority date	May 23, 2012
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

System and method for providing precision a self calibrating resistance circuit is described that provides for matching a reference resistor using dynamically configurable resistance networks. The resistor network is coupled to the connection, wherein the resistor network provides a configurable resistance across the connection. In addition, the resistor network comprises a digital resistor network and an analog resistor network. Also, the circuit includes control circuitry for configuring the configurable resistance based on a reference resistance of the reference resistor. The configurable resistance is configured by coarsely tuning the resistor network through the digital resistor network and fine tuning the resistor network through the analog resistor network.

First claim

The invention claimed is:

1. An apparatus for self-calibrating a configurable resistance on an integrated circuit, comprising:
a first power supply node;
a second power supply node;
a reference connection node;
a reference voltage source;
a voltage divider comprising:
the configurable resistance coupled between the first power supply node and the reference connection node,
wherein the configurable resistance comprises a digital resistor network coupled in parallel with an analog resistor network, and

a reference resistor coupled between the reference connection node and the second power supply node;

control circuitry coupled to the reference connection node and the reference voltage source for configuring the configurable resistance based on the resistance of the reference resistor by tuning the digital resistor network and by dynamically tuning the analog resistor network;
a register coupled to the control circuitry and to a plurality of digital control signals for storing the current data word and applying the combined state to the digital control signals;
a first amplifier comprising:
an output coupled to the control circuitry,
a first input coupled to the reference voltage source, and
a second input coupled to the reference connection node;

wherein the digital resistor network comprises a plurality of selectable resistive branches in parallel, each branch being coupled to one of the digital control signals and selected according to the state of that digital control signal;
wherein the resistance of the digital resistor network is determined by applying a data word comprising the desired combined state of the digital control signals to the digital control signals;
wherein the amplifier is used to compare the voltage on the reference connection node to the reference voltage and indicating the result to the control circuitry such that:
if the voltage on the reference connection node is higher than reference voltage the output of the amplifier is in a first logic state,
else the amplifier output is in a second logic state; and

wherein tuning the digital resistor network comprises:
(i) loading the data word corresponding to the highest tuned resistance into the register, applying the combined state to the digital resistor network, and observing the logic state of the output of the amplifier,
(ii) decreasing the resistance of the digital resistor network in a series of steps by loading a new data word into the resistor and applying the combined state to the digital control signals, wherein for each step:
a new data word is loaded into the register selecting an additional selectable resistive branch in parallel to the previously selected branch, and
the logic state of the output of the amplifier is observed until the logic state of the output of the amplifier changes,

(iii) selecting the last data word loaded prior to the logic state of the output of the amplifier changing, and
(iv) loading the selected data word into the register and applying the combined state to the digital control signals.

2. The apparatus of claim 1 :
wherein the analog resistor network comprises a variable resistive branch coupled to an analog control signal;
wherein the resistance of the analog resistor network is determined by the value of the analog signal;
wherein the output of the first amplifier is additionally coupled to the analog signal; and
wherein dynamically tuning the analog resistor network comprises:
(i) dynamically comparing the voltage on the reference connection node to the reference voltage, and
(ii) dynamically controlling the value of the analog signal using a feedback loop to tune the resistance of the analog resistor network such that the reference voltage and the voltage at the reference connection node are substantially equal.

3. The apparatus of claim 2 :
wherein the first power supply node is coupled to a positive voltage;
wherein the second power supply voltage is coupled to ground;
wherein the reference voltage source is a resistor divider; and
wherein the reference resistor is external to the integrated circuit.

4. The apparatus of claim 1 further comprising:
a second amplifier comprising:
an output coupled to an analog control signal,
a first input coupled to the reference voltage source, and
a second input coupled to the reference connection node;

wherein the analog resistor network comprises a variable resistive branch coupled to an analog control signal;
wherein the resistance of the analog resistor network is determined by the value of the analog signal; and
wherein dynamically tuning the analog resistor network comprises:
(i) dynamically comparing the voltage on the reference connection node to the reference voltage, and
(ii) dynamically controlling the value of the analog signal using a feedback loop to tune the resistance of the analog resistor network such that the reference voltage and the voltage at the reference connection node are substantially equal.

5. The apparatus of claim 4 :
wherein the first power supply node is coupled to a positive voltage;
wherein the second power supply voltage is coupled to ground;
wherein the reference voltage source is a resistor divider;
wherein the reference resistor is external to the integrated circuit;
wherein the first amplifier is a comparator; and
wherein the second amplifier is an operational amplifier.

Assignees

• Invensas Corp

Inventors

• Dicke Curtis
• Courville George
• Fisch David Edward
• Sandusky Randall
• Stalnaker Kent

Classifications

• G11C7/1057

  Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H01C10/50

  structurally combined with switching arrangements (H01C10/36 takes precedence) · CPC title

• H03K19/0005 Primary

  Modifications of input or output impedance · CPC title