Methods of operating memory devices and electronic systems

Patent metadata

Field	Value
Publication number	US-10164186-B2
Application number	US-201815869397-A
Country	US
Kind code	B2
Filing date	Jan 12, 2018
Priority date	Apr 5, 2007
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

Memory devices having memory cells comprising variable resistance material include an electrode comprising a single nanowire. Various methods may be used to form such memory devices, and such methods may comprise establishing contact between one end of a single nanowire and a volume of variable resistance material in a memory cell. Electronic systems include such memory devices.

First claim

What is claimed is:

1. A method of operating a memory device, the method comprising:
applying a first current to a volume of variable resistance material to write a first state to a memory cell, wherein applying the first current comprises:
applying the first current to an electrode of the memory cell;
increasing a density of the first current from a first current density to a second, higher current density; and
transmitting the first current having the second, higher current density through a single nanowire to the volume of variable resistance material; and

applying a second, different current to the volume of variable resistance material to write a second state to the memory cell.

2. The method of claim 1 , wherein increasing the density of the first current from the first current density to the second, higher current density comprises transmitting the first current through a generally conical catalytic structure having a base and a tip.

3. The method of claim 2 , wherein transmitting the first current through the generally conical catalytic structure comprises passing the first current through the base having a cross-sectional area and subsequently passing the first current through the tip having a cross-sectional area less than the cross-sectional area of the base.

4. The method of claim 2 , wherein transmitting the first current through the single nanowire to the volume of variable resistance material comprises passing the first current through the single nanowire as a sole pathway between the generally conical catalytic structure and the volume of variable resistance material.

5. The method of claim 1 , wherein:
applying the first current to the volume of variable resistance material includes providing a first voltage to induce the first current flowing through the volume of variable resistance material; and
applying the second, different current to the volume of variable resistance material includes providing a second, different voltage to induce the second, different current flowing through the volume of variable resistance material.

6. The method of claim 1 , wherein applying the second, different current to the volume of variable resistance material comprises applying a current that is greater than the first current.

7. The method of claim 1 , wherein applying the second, different current to the volume of variable resistance material comprises heating at least a portion of the volume of variable resistance material to induce a structural change in the at least a portion of the volume of variable resistance material.

8. The method of claim 7 , wherein heating the at least a portion of the volume of variable resistance material comprises altering a resistivity of the at least a portion of the volume of variable resistance material.

9. A method of operating a memory device, the method comprising:
applying a current to a first electrode to write a first phase to a memory cell;
increasing a density of the current as the current passes through the first electrode;
conducting the current through a sole pathway of a single nanowire to a volume of variable resistance material;
detecting a signal from the volume of variable resistance material with a second electrode located adjacent the volume of variable resistance material; and
applying another, different current to the first electrode to write a second, altered phase to the memory cell.

10. The method of claim 9 , further comprising detecting another, different signal from the volume of variable resistance material with the second electrode, the other, different signal being responsive at least in part to applying the other, different current.

11. The method of claim 9 , further comprising electrically communicating the signal from the second electrode to a conductive line.

12. The method of claim 9 , wherein applying the current to the first electrode comprises:
applying the current to a conductive pad;
conducting the current from the conductive pad directly to a generally conical catalytic structure; and
conducting the current from the generally conical catalytic structure directly to the single nanowire.

13. The method of claim 9 , wherein:
applying the current to the first electrode comprises conducting the current through a first conductive line to a region of the first conductive line comprising the first electrode; and
detecting the signal from the volume of variable resistance material with the second electrode comprises conducting the signal through the second electrode to a region of a second conductive line comprising the second electrode.

14. The method of claim 9 , wherein conducting the current through the sole pathway of the single nanowire to the volume of variable resistance material comprises passing the current through the single nanowire having an average diameter and subsequently conducting the current to the volume of variable resistance material having an average thickness of about twice the average diameter of the single nanowire.

15. The method of claim 9 , wherein:
detecting the signal from the volume of variable resistance material with the second electrode includes providing a first voltage between the first electrode and the second electrode to measure the current passing between the first electrode and the second electrode through the volume of variable resistance material; and
applying the other, different current to the first electrode includes providing a second, higher voltage between the first electrode and the second electrode to induce the other, different current to write the second, altered phase to the memory cell.

16. A method of operating an electronic system, the method comprising:
receiving at least one input with the electronic system;
alternating a state of at least one memory cell between a first state and a second state, comprising:
applying a first current to a volume of variable resistance material to read the state of the at least one memory cell; and
applying a second, higher current to the volume of variable resistance material to alter the state of the at least one memory cell, comprising passing the second, higher current through a catalytic structure to increase a density of the second, higher current and subsequently passing the second, higher current through a single nanowire to the volume of variable resistance material; and

producing at least one output with the electronic system responsive at least in part to reading the state of the at least one memory cell.

17. The method of claim 16 , further comprising selectively accessing the at least one memory cell with an access transistor, wherein selectively accessing the at least one memory cell includes performing a read operation or a write operation.

18. The method of claim 16 , further comprising processing at least one signal with an electronic signal processor in electrical communication with the at least one memory device, comprising assessing information responsive at least in part to reading the state of the at least one memory cell.

19. The method of claim 16 , wherein alternating the state of the at least one memory cell between the first state and the second state comprises alternating the state of the at least one memory cell between a first value of a binary code and a second value of the binary code, the second value of the binary code having a lower electrical resistivity than an electrical resistivity of the first value of the binary code.

20. The method of claim 16 , wherein passing the second, higher current t

Assignees

• Ovonyx Memory Tech Llc

Inventors

• Liu Jun
• Violette Michael P

Classifications

• H01L45/1675

  Electricity · mapped topic

• H01L45/06

  Electricity · mapped topic

• H01L45/065

  Electricity · mapped topic

• H01L45/126

  Electricity · mapped topic

• H01L45/144

  Electricity · mapped topic