Semiconductor device having first and second electrode layers electrically disconnected from each other by a slit

Patent metadata

Field	Value
Publication number	US-10164125-B2
Application number	US-201715689852-A
Country	US
Kind code	B2
Filing date	Aug 29, 2017
Priority date	Oct 17, 2011
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

A chip part includes a substrate, an element formed on the substrate, and an electrode formed on the substrate. A recess and/or projection expressing information related to the element is formed at a peripheral edge portion of the substrate.

First claim

What is claimed is:

1. A semiconductor device, comprising:
a silicon substrate;
an insulating film formed on the silicon substrate;
a first electrode layer formed on the insulating film, and being connected to the silicon substrate;
a second electrode layer formed on the insulating film, and being connected to the silicon substrate, the second electrode layer being electrically disconnected from the first electrode layer by a slit;
a first electrode connected to the first electrode layer;
a second electrode connected to the second electrode layer; and
a passivation film covering the first electrode layer and the second electrode layer, and not covering the first electrode and the second electrode,
wherein the first electrode layer has a first extending electrode portion and a second extending electrode portion, both of which extend toward the second electrode in a plan view, the first extending electrode portion and the second extending electrode portion being rimmed with the slit.

2. The semiconductor device according to claim 1 , wherein the second electrode layer extends toward the first electrode in a comb shape along the slit in the plan view.

3. The semiconductor device according to claim 2 , wherein the first extending electrode portion and the second extending electrode portion each has
an extending portion which linearly extends toward the second electrode in a first direction, and having a constant width in a second direction perpendicular to the first direction, and
a tip portion having a trapezoidal shape, in the plan view.

4. The semiconductor device according to claim 3 , wherein the constant width of the extending portion of the first extending electrode portion is a same width as the constant width of the extending portion of the second extending electrode portion.

5. The semiconductor device according to claim 4 , wherein a width of the slit between the first electrode layer and the second electrode layer facing each other in the plan view is equal to about 3 μm.

6. The semiconductor device according to claim 4 , further comprising:
a first opening formed on the insulation film to connect the first extending electrode portion to the silicon substrate; and
a second opening formed on the insulation film to connect the second extending electrode portion to the silicon substrate.

7. The semiconductor device according to claim 6 , wherein the constant width of the first extending electrode portion is greater than a width of the first opening in a direction parallel to the second direction, and the constant width of the second extending electrode portion is greater than a width of the second opening in a direction parallel to the second direction.

8. The semiconductor device according to claim 7 , further comprising first and second semiconductor regions in a surface layer of the silicon substrate, wherein
the silicon substrate has a first conductivity type, and each of the first and second semiconductor regions has a second conductivity type, and
the first and second openings are respectively disposed on the first and second semiconductor region.

9. The semiconductor device according to claim 8 , wherein a sum of widths of the first and second semiconductor regions is greater than a sum of widths of the first and second openings in a direction parallel to the second direction in the plan view.

10. The semiconductor device according to claim 9 , wherein the widths of the first and second semiconductor regions are set so that an Electro Static Discharge resistance of the semiconductor device is from about 8 kV to 16 kV.

11. The semiconductor device according to claim 8 , wherein the first conductivity type is a p type and the second conductivity type is an n type.

12. The semiconductor device according to claim 7 , wherein the first opening and the second opening each has a tapered side surface such that a size of the portion at an upper surface of the insulating film is greater than a size of the portion at a lower surface of the insulating film facing the silicon substrate in the plan view.

13. The semiconductor device according to claim 12 , wherein the first opening and the second opening each has an elliptical shape in the plan view.

14. The semiconductor device according to claim 5 , wherein the insulating film is made of oxide, and the passivation film is made of nitride.

Assignees

• Rohm Co Ltd

Inventors

• Yamamoto Hiroki

Classifications

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title

• H10W72/877

  Bump connectors and die-attach connectors · CPC title