Method for forming an implanted area for a heterojunction transistor that is normally blocked

US10164081B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10164081-B2
Application numberUS-201414787623-A
CountryUS
Kind codeB2
Filing dateApr 18, 2014
Priority dateApr 30, 2013
Publication dateDec 25, 2018
Grant dateDec 25, 2018

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  1. Title

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  2. Abstract

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  5. First independent claim

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Abstract

Official abstract text for this publication.

The invention relates to a method for manufacturing a heterojunction transistor ( 1 ), said method comprising the steps of: forming an implanted area ( 8 ) by ionically implanting magnesium, calcium, zinc, or fluorine in a first gallium nitride semiconductor layer ( 4 ), having a hexagonal crystalline structure, in the [0 0 0 1] orientation of said crystalline structure; forming a second semiconductor layer ( 6 ) on the first semiconductor layer so as to form an electron gas layer ( 5 ) at the interface between the first and second layers; and forming a control gate ( 75 ) over the second conductive layer ( 6 ) and vertically in line with the implanted area ( 8 ).

First claim

Opening claim text (preview).

The invention claimed is: 1. A heterojunction transistor fabrication process, comprising: forming a first semiconductor layer of gallium nitride of hexagonal crystal structure; forming a second semiconductor layer on the first semiconductor layer so as to form an electron gas layer at an interface between the first and the second semiconductor layers; then forming an implanted zone in the first semiconductor layer and an implanted zone in the second semiconductor layer by ion implanting magnesium, calcium, zinc or fluorine in the first semiconductor layer and the second semiconductor layer, wherein the ion implanting is in line with the [0001] direction of the gallium nitride hexagonal crystal structure, wherein the forming the implanted zone in the second semiconductor layer by the ion implanting induces an implantation density peak with a Gaussian distribution thicknesswise in the implanted zone of the second semiconductor layer; removing the implanted zone of the second semiconductor layer having the implantation density peak with the Gaussian distribution, and forming a control gate above the second semiconductor layer plumb with the implanted zone of the first semiconductor layer. 2. The process of claim 1 , further comprising activation annealing the implanted zone of the first semiconductor layer. 3. The process of claim 1 , wherein the first semiconductor layer is formed on a silicon substrate having a (111) crystal orientation. 4. The process of claim 1 , wherein an ion implantation energy of the ion implanting ranges from 1 to 10 keV. 5. The process of claim 1 , wherein the formation of the second semiconductor layer comprises growing the second semiconductor layer by epitaxy. 6. The process of claim 1 , wherein: the second semiconductor layer has a hexagonal crystal structure; and the forming the implanted zone in the second semiconductor layer by ion implanting occurs in line with a [0001] direction of the hexagonal crystal structure of the second semiconductor layer. 7. The process of claim 1 , wherein the second semiconductor layer formed is a binary group-III nitride alloy. 8. The process of claim 1 , wherein the second semiconductor layer formed is a ternary group-III nitride alloy. 9. The process of claim 1 , wherein the implanted zone in the first semiconductor layer is formed by ion implanting magnesium in the first semiconductor layer and the implanted zone in the first semiconductor layer has a magnesium density ranging from 10 16 to 10 19 cm −3 over a thickness at least equal to 15 nm starting from the interface between the first and second semiconductor layers. 10. The process of claim 1 , wherein the implanted zone in the first semiconductor layer includes at least 30% of a total amount of dopant introduced during the forming the implanted zone in the first semiconductor layer by ion implanting. 11. The process of claim 1 , wherein the second semiconductor layer has a [0001] direction coincident with the [0001] direction of the first semiconductor layer. 12. The process of claim 1 , wherein the forming the implanted zone in the first semiconductor layer by ion implanting is carried out by ion implanting the magnesium, the calcium, the zinc or the fluorine at an angle smaller than or equal to 2° to the [0001] direction of the first semiconductor layer. 13. The process of claim 1 , wherein the forming the implanted zone in the first semiconductor layer by ion implanting the magnesium, the calcium, the zinc or the fluorine is carried out at an angle smaller than or equal to 1° in the [0001] direction of the first semiconductor layer. 14. The process of claim 1 , wherein the forming the implanted zone in the first semiconductor layer by ion implanting the magnesium, the calcium, the zinc or the fluorine includes ion implanting at an implantation energy of between 1 and 10 keV. 15. The process of claim 1 , wherein the forming the implanted zone in the first semiconductor layer by ion implanting the magnesium, the calcium, the zinc or the fluorine is carried out at an implantation energy of between 1 and 5 keV. 16. The process of claim 1 , wherein the forming the implanted zone in the first semiconductor layer by ion implanting the magnesium, the calcium, the zinc or the fluorine is carried out at an implantation energy of between 5 and 10 keV. 17. The process of claim 1 , wherein the forming the implanted zone in the second semiconductor layer by ion implanting is carried out in line with a [0001] direction of the crystal structure of the second semiconductor layer by orienting the ion implanting less than 1° to the [0001] direction of the crystal structure of the first and the second semiconductor layers. 18. The process of claim 17 , wherein the second semiconductor layer is AlGaN.

Assignees

Inventors

Classifications

  • of Group III-V semiconductors · CPC title

  • into Group III-V semiconductors · CPC title

  • of electrically active species · CPC title

  • Controlling the interface between substrate and epitaxial layer, e.g. by ion implantation followed by annealing · CPC title

  • Crystal orientation · CPC title

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What does patent US10164081B2 cover?
The invention relates to a method for manufacturing a heterojunction transistor ( 1 ), said method comprising the steps of: forming an implanted area ( 8 ) by ionically implanting magnesium, calcium, zinc, or fluorine in a first gallium nitride semiconductor layer ( 4 ), having a hexagonal crystalline structure, in the [0 0 0 1] orientation of said crystalline structure; forming a second semico…
Who is the assignee on this patent?
Commissariat Energie Atomique, Commissariat Energie Atomique
What technology area does this patent fall under?
Primary CPC classification H01L29/7787. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 25 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).