Semiconductor device having trench capacitor structure integrated therein
US-9608130-B2 · Mar 28, 2017 · US
Deep trench capacitor with a filled trench and a doped region serving as a capacitor electrode
US10164005B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-10164005-B2 |
| Application number | US-201615072906-A |
| Country | US |
| Kind code | B2 |
| Filing date | Mar 17, 2016 |
| Priority date | Mar 17, 2016 |
| Publication date | Dec 25, 2018 |
| Grant date | Dec 25, 2018 |
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- Title
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- Abstract
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Abstract
Official abstract text for this publication.
The present disclosure provides a semiconductor structure which comprises a semiconductive substrate and a doped region in the semiconductive substrate. The doped region has a conductivity type opposite to the semiconductive substrate. The semiconductor structure also includes a capacitor in the doped region where the capacitor comprises a plurality of electrodes and the plurality of electrodes are insulated with one another. The semiconductor structure further includes a plug in the capacitor and surrounded by the plurality of electrodes.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor structure, comprising: a semiconductive substrate; a doped region in the semiconductive substrate, the doped region having a conductivity type opposite to the conductivity type of the semiconductive substrate; a capacitor in the doped region, the capacitor comprising a plurality of electrodes and the plurality of electrodes being insulated from one another; a first dielectric disposed on one of the plurality of electrodes; and a multi-layer structure extending within the capacitor and surrounded by the first dielectric, wherein the multi-layer structure comprises a second dielectric contacting the first dielectric and exposing a portion of the first dielectric. 2. The semiconductor structure of claim 1 , wherein the multi-layer structure further includes a conductive material surrounded by the second dielectric. 3. The semiconductor structure of claim 1 , wherein the multi-layer structure is electrically insulated from the plurality of electrodes. 4. The semiconductor structure of claim 1 , wherein the multi-layer structure is electrically coupled to one of the plurality of electrodes. 5. The semiconductor structure of claim 1 , wherein the multi-layer structure further includes a same material as one of the plurality of electrodes. 6. The semiconductor structure of claim 1 , wherein each of the plurality of electrodes is extending over a portion of a top surface of the semiconductive substrate. 7. The semiconductor structure of claim 1 , wherein the doped region is electrically insulated from one of the plurality of electrodes. 8. The semiconductor structure of claim 1 , further comprising an interconnect structure comprising a plurality of conductive vias electrically coupled to the doped region and each of the plurality of electrodes, respectively. 9. The semiconductor structure of claim 1 , wherein the multi-layer structure further comprises tungsten. 10. The semiconductor structure of claim 1 , wherein the multi-layer structure has an aspect ratio from about 20 to about 80.
Assignees
Inventors
Classifications
- H10W20/496Primary
Capacitor integral with wiring layers · CPC title
Electricity · mapped topic
- H01L28/90Primary
Electricity · mapped topic
Resistors, capacitors or inductors · CPC title
- H10D1/716Primary
having vertical extensions · CPC title
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Frequently asked questions
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- What does patent US10164005B2 cover?
- The present disclosure provides a semiconductor structure which comprises a semiconductive substrate and a doped region in the semiconductive substrate. The doped region has a conductivity type opposite to the semiconductive substrate. The semiconductor structure also includes a capacitor in the doped region where the capacitor comprises a plurality of electrodes and the plurality of electrodes…
- Who is the assignee on this patent?
- Taiwan Semiconductor Mfg Co Ltd
- What technology area does this patent fall under?
- Primary CPC classification H10W20/496. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Dec 25 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 3 related publications on this page (citations in our corpus or others sharing the same primary CPC).