Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices

Patent metadata

Field	Value
Publication number	US-10163826-B2
Application number	US-201715787041-A
Country	US
Kind code	B2
Filing date	Oct 18, 2017
Priority date	Mar 13, 2007
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed. In one embodiment, a system comprises a semiconductor component including an interposer substrate, a microelectronic die over the interposer substrate, and a connection structure composed of a volume of solder material between the interposer substrate and the microelectronic die. The connection structure can include at least one of (a) a single, unitary structure covering approximately all of the back side of the microelectronic die, and (b) a structure electrically isolated from internal active features of the microelectronic die. In some embodiments, the connection structure can be positioned to provide generally consistent stress distribution within the system.

First claim

We claim:

1. A system, comprising:
at least one of a processor and a memory device, wherein at least one of the processor and the memory device includes a semiconductor component comprising—
an interposer substrate including a plurality of first terminals;
a microelectronic die having an active side, a back side opposite the active side and facing toward the interposer substrate, integrated circuitry, and a plurality of second terminals at the active side and electrically coupled to the integrated circuitry, and wherein the second terminals at the active side of the microelectronic die are electrically coupled to corresponding first terminals of the interposer substrate with a plurality of wire bonds; and
a connection structure composed of a volume of solder material between the interposer substrate and the microelectronic die, wherein the connection structure is attached to both the interposer substrate and the back side of the microelectronic die,
wherein the connection structure includes at least one of (a) a single, unitary structure covering approximately all of the back side of the microelectronic die, and (b) a structure electrically isolated from internal active features of the microelectronic die.

2. The system of claim 1 wherein the microelectronic die is electrically coupled to one or more grounding structures of the interposer substrate via the connection structure.

3. The system of claim 1 wherein the volume of solder material comprises a plurality of pre-formed solder balls, and wherein the solder balls do not transmit signals between the microelectronic die and the interposer substrate.

4. The system of claim 1 wherein the microelectronic die further comprises a conductive layer at the back side of the microelectronic die and in contact with the connection structure.

5. The system of claim 1 wherein the volume of solder material between the interposer substrate and the microelectronic die has a generally uniform thickness.

6. The system of claim 1 , further comprising an encapsulant over the interposer substrate and at least partially covering the microelectronic die, first terminals, second terminals, and wire bonds.

7. The system of claim 1 wherein the connection structure is composed of SnAgCu, SnAg, or SnAu solder.

8. The system of claim 1 wherein the connection structure is formed of a lead-free solder material.

9. The system of claim 1 wherein the microelectronic die comprises one of an imager, a filter, or a sensor.

Assignees

• Micron Technology Inc

Inventors

• Schwab Matt E
• Corisis David J
• Brooks J Michael

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/15

  on active surfaces of flip-chip devices, e.g. underfills · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title