Semiconductor package with multiple molding routing layers and a method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10163658-B2
Application number	US-201715667433-A
Country	US
Kind code	B2
Filing date	Aug 2, 2017
Priority date	Nov 10, 2015
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

Embodiments of the present invention are directed to a method of manufacturing a semiconductor package with an internal routing circuit. The internal routing circuit is formed from multiple molding routing layers in a plated and etched copper terminal semiconductor package by using a laser to activate areas of each molding compound layer of the semiconductor package. Each compound filler in the molding compound layer has a metal interior and an insulating outermost shell. The activated molding compound areas in the molding compound layer become metallized in an electroless plating solution to build conductive paths on the molding compound surface, while properties of non-activated molding compound areas are not changed.

First claim

We claim:

1. A method of manufacturing semiconductor devices that each includes a plurality of conductive routing layers, comprising:
obtaining an etched and plated leadframe that includes a plurality of copper routing circuits and a plurality of package terminals, wherein the plurality of copper routing circuits forms a copper leadframe routing layer;
forming at least one metal plated routing layer on top of the copper leadframe routing layer, wherein each of the at least one metal plated routing layer is formed by:
coupling a plurality of interconnections with routing circuits associated with a previous routing layer that is directly beneath a current metal plated routing layer being formed;
forming an intermediary insulation layer on top of the previous routing layer, wherein the plurality of interconnections protrudes from a top surface of the intermediary insulation layer;
removing areas of the intermediary insulation layer, thereby forming cavities in the intermediary insulation layer and exposing metal at a nuclei of the fillers that are located at boundaries of the cavities; and
adhering a metal layer in the cavities of the intermediary insulation layer to form a plurality of metal routing circuits that is included in the current metal plated routing layer;

coupling a plurality of dies with a topmost metal plated routing layer;
encapsulating the plurality of dies and the topmost metal routing layer with a topmost insulation layer;
etching away exposed copper at a bottom of the leadframe, thereby isolating the plurality of package terminals and exposing the plurality of copper routing circuits at the bottom of the leadframe;
encapsulating the plurality of exposed copper routing circuits at the bottom of the leadframe with a bottommost insulation layer; and
performing a cut-through procedure to singulate the semiconductor packages from each other.

2. The method of claim 1 , wherein obtaining an etched and plated leadframe includes:
etching a copper substrate to form the plurality of copper routing circuits at a top surface of the copper substrate; and
plating a plurality of areas on surfaces of the copper substrate, thereby resulting in the etched and plated leadframe, wherein the plurality of areas includes bottom plated areas that eventually form the plurality of package terminals and includes top plated areas that are on the plurality of copper routing circuits.

3. The method of claim 2 , wherein material of the intermediary insulation layer is a laser direct structuring molding compound that has a transforming property when blasted by a laser.

4. The method of claim 3 , wherein the exposed metal fillers are fillers in the intermediary insulation layer, wherein the fillers have portions of their insulation outermost shells removed.

5. The method of claim 4 , wherein metal at the nuclei of the fillers are exposed.

6. The method of claim 5 , wherein each of the at least one metal plated routing layer is further formed by, after adhering a metal layer in the cavities of the intermediary insulation layer, obtaining a desired thickness of the metal routing circuits whereby metal is plated on metal.

7. The method of claim 6 , wherein the desired thickness of the metal routing circuits is obtained via an electroless plating process, wherein the electroless plating process includes repeating the adhering step in one or more loops.

8. A method of manufacturing semiconductor devices that each includes a plurality of conductive routing layers, comprising:
obtaining an etched and plated leadframe that includes a plurality of copper routing circuits and a plurality of package terminals, wherein the plurality of copper routing circuits forms a copper leadframe routing layer;
forming at least one metal plated routing layer on top of the copper leadframe routing layer, wherein each of the at least one metal plated routing layer is formed by:
coupling a plurality of interconnections with routing circuits associated with a previous routing layer that is directly beneath a current metal plated routing layer being formed;
forming an intermediary insulation layer on top of the previous routing layer, wherein the plurality of interconnections protrudes from a top surface of the intermediary insulation layer;
removing areas of the intermediary insulation layer, thereby forming cavities in the intermediary insulation layer and exposing metal at a nuclei of the fillers that are located at boundaries of the cavities, wherein the exposed metal fillers are fillers in the intermediary insulation layer that have sides of insulation outmost shells of the fillers that are removed; and
adhering a metal layer in the cavities of the intermediary insulation layer to form a plurality of metal routing circuits that is included in the current metal plated routing layer;

coupling a plurality of dies with a topmost metal plated routing layer;
encapsulating the plurality of dies and the topmost metal routing layer with a topmost insulation layer;
etching away exposed copper at a bottom of the leadframe, thereby isolating the plurality of package terminals and exposing the plurality of copper routing circuits at the bottom of the leadframe;
encapsulating the plurality of exposed copper routing circuits at the bottom of the leadframe with a bottommost insulation layer; and
performing a cut-through procedure to singulate the semiconductor packages from each other.

9. The method of claim 8 , wherein material of the intermediary insulation layer is a laser direct structuring molding compound that has a transforming property when blasted by a laser.

10. The method of claim 8 , wherein each of the at least one metal plated routing layer is further formed by, after adhering a metal layer in the cavities of the intermediary insulation layer, obtaining a desired thickness of the metal routing circuits whereby metal is plated on metal.

11. The method of claim 10 , wherein the desired thickness of the metal routing circuits is obtained via an electroless plating process, wherein the electroless plating process includes repeating the adhering step in one or more loops.

12. The method of claim 8 , wherein portions of the copper routing circuits are plated.

13. The method of claim 8 , wherein exposed surfaces of the package terminals are flush with a bottom surface of the bottommost insulation layer.

Assignees

• Utac Headquarters Pte Ltd
• Utac Headquarters Pte Ltd

Inventors

• Sirinorakul Saravuth
• Yenrudee Suebphong

Classifications

• H10W72/522

  Multilayered bond wires, e.g. having a coating concentric around a core · CPC title

• H10W72/552

  comprising metals or metalloids, e.g. silver · CPC title

• H10W72/5522

  comprising gold [Au] · CPC title

• H10W72/0198

  batch processes · CPC title

• H10W70/457

  of metallic layers on leadframes · CPC title