Adaptive memory address scanning based on surface format for graphics processing

Patent metadata

Field	Value
Publication number	US-10163180-B2
Application number	US-201514699806-A
Country	US
Kind code	B2
Filing date	Apr 29, 2015
Priority date	Apr 29, 2015
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

This disclosure describes an adaptive memory address scanning technique that defines an address scanning pattern, to be used for a particular surface, based on one or more properties of the surface. In addition, a number, shape, and arrangement of sub-primitives of a surface to process in parallel may be determined. In one example of the disclosure, a memory accessing method for graphics processing comprises, determining, by a graphics processing unit (GPU), properties of a surface, determining, by the GPU, a memory address scanning technique based on the determined properties of the surface, and performing, by the GPU, at least one of a read or a write of data associated with the surface in a memory based on the determined memory address scanning technique.

First claim

What is claimed is:

1. A memory accessing method for graphics processing, the method comprising:
determining, by a graphics processing unit (GPU), properties of a format of a surface in a memory, wherein the surface includes pixel values of an image, and wherein the properties of the format of the surface include at least one of a surface height, a surface width, use of pixel compression, or use of multi-sample anti-aliasing;
dividing the surface into sub-primitives based on the properties of the format of the surface;
determining, by the GPU, memory address scanning techniques for the sub-primitives based on the properties of the format of the surface, wherein the GPU determines the memory address scanning techniques such that at least some of the sub-primitives are associated with different memory address scanning techniques, and
wherein the memory address scanning techniques define a memory addressing patterns; and
performing, by the GPU, at least one of a read or a write of data associated with the surface in the memory based on the determined memory address scanning techniques.

2. The method of claim 1 , wherein dividing the surface into sub-primitives based on the properties of the format of the surface comprises:
determining, by the GPU, a number and a shape of sub-primitives in which to divide the surface based on the properties of the format of the surface; and
dividing, by the GPU, the surface into one or more sub-primitives based on the determined number and shape of sub-primitives.

3. The method of claim 2 , wherein determining the shape of sub-primitives in which to divide the surface based on the properties of the format of the surface further comprises:
determining, by the GPU, a shape of an arrangement of the determined number of sub-primitives based on the properties of the format of the surface; and
dividing, by the GPU, the surface into the determined shape of the arrangement of the determined number of sub-primitives.

4. The method of claim 2 , wherein performing the at least one of the read or the write of the data associated with the surface comprises:
performing, by the GPU, the at least one of the read or the write of data associated with each of the one or more sub-primitives.

5. The method of claim 4 , further comprising:
determining a number of parallel address scanning engines used to perform the at least one of the read or the write of data based on the properties of the format of the surface; and
performing the at least one of the read or the write of the data with the determined number of parallel address scanning engines.

6. The method of claim 4 , wherein performing the at least one of the read or the write of data associated with each of the one or more sub-primitives comprises performing the at least one of the read or the write of data associated with each of the one or more sub-primitives in parallel.

7. The method of claim 1 , wherein the memory address scanning techniques include a first memory addressing pattern starting from an upper left corner of the sub-primitives, a second memory addressing pattern starting from an upper right corner of the sub-primitives, a third memory addressing pattern starting from a lower left corner the sub-primitives, and a fourth memory address pattern starting from a lower right corner of the sub-primitives.

8. The method of claim 1 , wherein the memory address scanning techniques include a first horizontal memory addressing pattern proceeding in a forward direction, and a second horizontal memory addressing pattern proceeding in a reverse direction.

9. An electronic device configured to access memory for graphics processing, the electronic device comprising:
a memory configured to store data associated with a surface in a memory; and
a graphics processing unit (GPU) in communication with the memory, the GPU configured to:
determine properties of a format of the surface, wherein the surface includes pixel values of an image, and wherein the properties of the format of the surface include at least one of a surface height, a surface width, use of pixel compression, or use of multi-sample anti-aliasing;
divide the surface into sub-primitives based on the properties of the format of the surface;
determine memory address scanning techniques for the sub-primitives based on the properties of the format of the surface, wherein the GPU determines the memory address scanning techniques such that at least some of the sub-primitives are associated with different memory address scanning techniques, and
wherein the memory address scanning techniques define memory addressing patterns; and
perform at least one of a read or a write of the data associated with the surface in the memory based on the determined memory address scanning techniques.

10. The electronic device of claim 9 , wherein to divide the surface into sub-primitives based on the properties of the format of the surface the GPU is further configured to:
determine a number and a shape of sub-primitives in which to divide the surface based on the properties of the format of the surface; and
divide the surface into one or more sub-primitives based on the determined number and the shape of sub-primitives.

11. The electronic device of claim 10 , wherein to determine the shape of sub-primitives in which to divide the surface based on the properties of the format of the surface, the GPU is further configured to:
determine a shape of an arrangement of the determined number of sub-primitives based on the properties of the format of the surface; and
divide the surface into the determined shape of the arrangement of the determined number of sub-primitives.

12. The electronic device of claim 10 , wherein to perform the at least one of the read or the write of the data associated with the surface, the GPU is further configured to:
perform the at least one of the read or the write of data associated with each of the one or more sub-primitives.

13. The electronic device of claim 12 , wherein the GPU is further configured to:
determine a number of parallel address scanning engines of the GPU used to perform the at least one of the read or the write of data based on the properties of the format of the surface; and
perform the at least one of the read or the write of the data with the determined number of parallel address scanning engines.

14. The electronic device of claim 12 , wherein to perform the at least one of the read or the write of data associated with each of the one or more sub-primitives, the GPU is further configured to:
perform the at least one of the read or the write of data associated with each of the one or more sub-primitives in parallel.

15. The electronic device of claim 9 , wherein the memory and GPU are part of a mobile communications device.

16. The electronic device of claim 15 , further comprising:
a processor executing an application that causes the GPU to render the surface; and
a display configured to display the rendered surface in accordance with the application.

17. The electronic device of claim 9 , wherein the memory address scanning techniques include a first memory addressing pattern starting from an upper left corner of the sub-primitives, a second memory addressing pattern starting from an upper right corner of the sub-primitives, a third memory addressing pattern starting from a lower left corner the sub-primitives, and a fourth memory address pattern starting from a lower right corner of the sub-primitives.

18. The electronic device of claim 9 , wherein the memory address scan

Assignees

• Qualcomm Inc

Inventors

• Liang Jian
• Huang Minjie
• Wang Chunlin

Classifications

• G06T11/40

  Filling planar surfaces by adding surface attributes, e.g. adding colours or textures · CPC title

• G06T1/60 Primary

  Memory management · CPC title

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06T2200/28

  involving image processing hardware · CPC title