Dynamic logic memcap

Patent metadata

Field	Value
Publication number	US-10162263-B2
Application number	US-201515547105-A
Country	US
Kind code	B2
Filing date	Apr 27, 2015
Priority date	Apr 27, 2015
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

An integrated circuit may include a substrate with a plurality of transistors formed in the substrate. The plurality of transistors may be coupled to a first metal layer formed over the plurality of transistors. A plurality of high dielectric nanometer capacitors may be formed of memristor switch material between the first metal layer and a second metal layer formed over the plurality of high dielectric capacitors. The plurality of high dielectric capacitors may operate as memory storage cells in dynamic logic.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a substrate with one or more transistors formed in the substrate, the one or more transistors coupled to a first metal layer formed over the one or more transistors; and
a plurality of memcapacitors formed of memristor switch material creating an active region between the first metal layer and a second metal layer formed over the plurality of memcapacitors, wherein the plurality of memcapacitors are to operate as memory storage cells in dynamic logic;
wherein the dynamic logic is to operate as a set of shift registers; and
wherein the set of shift registers have set/reset functionality by programming the memcapacitors which function as memristors.

2. The integrated circuit of claim 1 wherein the memristor switch material active region is formed of memristor switch elemental or compound semiconductor and doped with mobile dopants to allow for memristor operation.

3. The integrated circuit of claim 1 wherein the dynamic logic is to operate as a set of shift registers.

4. The integrated circuit of claim 1 wherein the plurality of memcapacitors are formed of a stack of first metal oxide and a first metal/second metal transition layer.

5. The integrated circuit of claim 1 wherein the plurality of memcapacitors has a dielectric constant of at least 6.

6. The integrated circuit of claim 1 wherein the plurality of memcapacitors have a thickness less than 100 nanometers.

7. The integrated circuit of claim 1 wherein the plurality of memcapacitors have an area less than 400 micro-meters 2 .

8. The integrated circuit of claim 1 wherein the one or more transistors are NMOS transistors.

9. The integrated circuit of claim 1 , wherein the memristor switch material is formed of memristor switch oxide of the first metal layer and additionally operational as memristors.

10. The integrated circuit of claim 9 , further comprising a second number of transistors coupled between respective plurality of memcapacitors and a programming source to allow for programming the memristors.

11. An integrated circuit, comprising:
a substrate with one or more transistors formed in the substrate, the one or more transistors coupled to a first metal layer formed over the one or more transistors; and
a plurality of memcapacitors formed of memristor switch material creating an active region between the first metal layer and a second metal layer formed over the plurality of memcapacitors, wherein the plurality of memcapacitors are to operate as memory storage cells in dynamic logic;
wherein the dynamic logic is to operate as a set of shift registers; and
wherein the set of shift registers is to control a set of fluid jet resistors.

12. An integrated circuit, comprising: a substrate with a transistor formed in the substrate, the transistor coupled to a first metal layer formed over the transistor; and a memcapacitor formed of memristor switch material creating an active region between the first metal layer and a second metal layer formed over the memcapacitor, the memcapacitor being formed of a stack of first metal oxide and a first metal/second metal transition layer wherein the memcapacitor is a memory storage cell in a dynamic logic circuit, and wherein the dynamic logic circuit is to operate as a set of shift registers; and wherein the dynamic logic circuit operating as a set of shift registers is to control a set of fluid jet resistors.

13. An integrated circuit, comprising: a substrate with a transistor formed in the substrate, the transistor coupled to a first metal layer formed over the transistor and a memcapacitor formed of memristor switch material creating an active region between the first metal layer and a second metal layer formed over the memcapacitor, the memcapacitor being formed of a stack of first metal oxide and a first metal/second metal transition layer wherein the memcapacitor is a memory storage cell in a dynamic logic circuit, and wherein the dynamic logic circuit is to operate as a set of shift registers; and wherein the set of shift registers have set/reset functionality by programming the memcapacitors which act as memristors.

14. A method of forming an integrated circuit, comprising:
depositing an insulator layer over a number of transistors formed in a substrate interconnected by a first metal layer;
masking and etching the insulator layer to define a set of vias and a set of areas and locations of a first plate of a plurality of the high-k dielectric nanometer memcaps for dynamic logic thereby exposing the first metal layer;
applying a memristor switch material (MSM) layer in the etched insulator layer above the exposed first metal layer to form a nanometer thick layer of high quality dielectric material creating an active region;
depositing a transition layer of a combination of the first metal layer and a second metal layer over the MSM layer;
masking and etching the transition layer and the MSM layer to remove the transition layer and the MSM layer within the set of vias and to not remove them in the location for a second plate of the high-k dielectric nanometer memcaps; and
depositing the second metal layer over the transition layer to define the area and location of the second plate.

15. The method of claim 14 , further comprising the step of doping the MSM layer active region with material vacancies.

16. The method of claim 15 wherein the applying of the MSM layer is done to a thickness of less than 100 nm.

Assignees

• Hewlett Packard Development Co

Inventors

• Ge Ning
• Li Zhiyong
• Yang Jianhua
• Williams R Stanley

Classifications

• G11C19/28

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G11C2213/31

  Material having complex metal oxide, e.g. perovskite structure · CPC title

• H01L45/1233

  Electricity · mapped topic

• B41J2/14129

  Layer structure · CPC title

• H01L45/1683

  Electricity · mapped topic