MEMS device and process for RF and low resistance applications

Patent metadata

Field	Value
Publication number	US-10160635-B2
Application number	US-201715477202-A
Country	US
Kind code	B2
Filing date	Apr 3, 2017
Priority date	Nov 28, 2012
Publication date	Dec 25, 2018
Grant date	Dec 25, 2018

Abstract

MEMS device for low resistance applications are disclosed. In a first aspect, the MEMS device comprises a MEMS wafer including a handle wafer with one or more cavities containing a first surface and a second surface and an insulating layer deposited on the second surface of the handle wafer. The MEMS device also includes a device layer having a third and fourth surface, the third surface bonded to the insulating layer of the second surface of handle wafer; and a metal conductive layer on the fourth surface. The MEMS device also includes CMOS wafer bonded to the MEMS wafer. The CMOS wafer includes at least one metal electrode, such that an electrical connection is formed between the at least one metal electrode and at least a portion of the metal conductive layer.

First claim

What is claimed is:

1. A method, comprising:
depositing a first metal layer directly onto a silicon device layer;
forming a piezoelectric layer on the first metal layer;
depositing a second metal layer onto the piezoelectric layer;
depositing a germanium layer onto the second metal layer; and
bonding the germanium layer to a CMOS wafer.

2. The method of claim 1 , wherein the depositing the first metal layer comprises depositing the first metal layer onto a silicon-on-insulator wafer.

3. The method of claim 1 , wherein the depositing the first metal layer comprises depositing a molybdenum layer onto the silicon device layer.

4. The method of claim 1 , wherein the depositing the first metal layer comprises depositing a platinum layer onto the silicon device layer.

5. The method of claim 1 , wherein the forming the piezoelectric layer comprises performing an etching process associated with the first metal layer.

6. The method of claim 1 , wherein the forming the piezoelectric layer comprises forming an aluminum nitride layer.

7. The method of claim 1 , wherein the forming the piezoelectric layer comprises forming a lead zirconate titanate layer.

8. The method of claim 1 , wherein the depositing the second metal layer comprises depositing an aluminum layer onto the silicon device layer.

9. The method of claim 1 , wherein the depositing the germanium layer comprises forming one or more germanium bonding pads.

10. The method of claim 1 , wherein the boding comprises bonding the germanium layer to one or more aluminum pads of the CMOS wafer.

Assignees

• Invensense Inc

Inventors

• Daneman Michael J
• Lim Martin
• Li Xiang
• Hung Li-Wen

Classifications

• B81C3/001

  Bonding of two components · CPC title

• B81C2201/019

  Bonding or gluing multiple substrate layers · CPC title

• B81B2207/07

  Interconnects · CPC title

• B81B3/0086 Primary

  Electrical characteristics, e.g. reducing driving voltage, improving resistance to peak voltage · CPC title