Composite circuit board and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-10159149-B2
Application number	US-201715581947-A
Country	US
Kind code	B2
Filing date	Apr 28, 2017
Priority date	Dec 29, 2016
Publication date	Dec 18, 2018
Grant date	Dec 18, 2018

Abstract

A composite circuit board includes an insulation layer, an inner circuit layer, a first conductive layer and a second conductive layer embedded in the insulation layer, a third conductive layer and a fourth conductive layer formed on opposite surfaces of the insulation layer. The third conductive layer electrically connects with the first conductive layer. The fourth conductive layer electrically connects with the second conductive layer. The inner circuit layer is in a middle portion of the insulation layer. The first conductive layer and the second conductive layer respectively forms on opposite sides of the inner circuit layer. The insulation layer forms a plurality of first through holes between the first conductive layer and the inner circuit layer, a plurality of second through holes between the second conductive layer and the inner circuit layer.

First claim

What is claimed is:

1. A method of manufacturing a composite circuit board, comprising the steps of: providing a first plate; forming a first photosensitive resin layer and a bearing layer on opposite surfaces of the first plate; patterning the first photosensitive resin layer to form a plurality of first gaps by exposure imaging; etching a portion of the first plate exposed from the plurality of first gaps to form a plurality of spacings on the first plate, thereby the first plate forms an inner circuit layer; removing the remainder first photosensitive resin layer from the inner circuit layer; forming a second photosensitive resin layer on a surface of the inner circuit layer, then removing the bearing layer on another surface of the inner circuit layer and further forming the second photosensitive resin layer on another surface of the inner circuit layer; patterning the second photosensitive resin layer to form a plurality of second gaps by exposure imaging, at the same time, curing the second photosensitive resin layer; forming a first seed layer on a surface of the second photosensitive resin layer and the surface around the plurality of the second gaps; forming a third photosensitive resin layer on a surface of the first seed layer; patterning the third photosensitive resin layer to form a plurality of third gaps through the way of exposure imaging; plating copper in the plurality of the third gaps and the plurality of second gaps to form a first conductive layer and a second conductive layer; removing the remainder third photosensitive resin layer and the first seed layer corresponding to the remainder third photosensitive resin layer; forming a fourth photosensitive resin layer on the first conductive layer and the second conductive layer; patterning the fourth photosensitive resin layer to form a plurality of fourth gaps through the way of exposure imaging, at the same time curing the fourth photosensitive resin layer: forming a second seed layer on a surface of the fourth photosensitive resin layer and the surface around the plurality of the fourth gaps; forming a fifth photosensitive resin layer on a surface of the second seed layer; patterning the fifth photosensitive resin layer to form a plurality of fifth gaps; plating copper in the plurality of fifth gaps and the fourth gaps to form a third conductive layer and a fourth conductive layer; removing the remainder fifth photosensitive resin layer and the second seed layer correspondingly to the remainder fifth photosensitive resin layer.

2. The method of claim 1 , wherein a depth of the plurality of spacings is equal to a thickness of the first plate, the plurality of the spacings corresponds to the plurality of the first gaps, and a bore diameter of the plurality of spacings is equal to a bore diameter of a first gap.

3. The method of claim 1 , wherein while forming the first seed layer, the inner circuit layer is exposed from the plurality of the second gaps.

4. The method of claim 1 , wherein the third photosensitive resin layer is spaced from the inner circuit layer by the plurality of the second gaps.

5. The method of claim 4 , wherein the plurality of third gaps corresponding to the second gaps is connected to the second gaps.

6. The method of claim 1 , wherein the first conductive layer comprises a plurality of first conductive portions spaced from each other, the second conductive layer comprises a plurality of second conductive portions spaced from each other.

7. The method of claim 1 , wherein the fourth photosensitive resin layer covers the first conductive layer and the second conductive layer.

8. The method of claim 1 , further comprising filling an insulation colloid on an outer surface of the third conductive layer and the fourth conductive layer, and curing the insulation colloid to form an encapsulation layer.

9. The method of claim 8 , wherein the encapsulation layer covers the third conductive layer and the fourth conductive layer.

Assignees

• Hongqisheng Prec Electronics Qinhuangdao Co Ltd
• Fukui Prec Component Shenzhen
• Hongqisheng Prec Electronics Qinhuangdao Co
• Avary Holding Shenzhen Co Ltd

Inventors

• Hu xian-qin
• Yang Mei
• Li Cheng-Jia

Classifications

• H05K3/4691 Primary

  Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers · CPC title

• H05K3/185

  by making a catalytic pattern by photo-imaging · CPC title

• H05K3/429

  Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers · CPC title

• H05K2203/052

  Magnetographic patterning · CPC title

• H05K2201/096

  Vertically aligned vias, holes or stacked vias · CPC title